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參數(shù)資料
| 型號(hào)： | MCZ33742SEG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類(lèi)： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁(yè)數(shù)： | 47/65頁(yè) |
| 文件大?。?/td> | 1158K |
| 代理商： | MCZ33742SEG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
47
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
TIMING REGISTER (TIM1 / 2)
Tables 30
through
34
contain the Timing Register information. The TIM register is composed of two sub registers:
TIM1 — Controls the watchdog timing selection as well as either the watchdog window or the watchdog time-out option
(
Figure 28
and
Figure 29
, respectively). TIM1 is selected when bit D3 is 0 (
Table 30
). Watchdog timing characteristics are
described in
Table 31
.
TIM2 — Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on
or off. TIM2 is selected when bit D3 is 1 (
Table 32
).
Figure 30
, page
49
, describes HS
operation when cyclic sense is selected
Cyclic sense timing characteristics are described in
Table 34
, page
49
.
Both subregisters also report the CANL and TXD diagnostics.
Table 28. Wake-Up Register Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0 L1 : L1 L2 Config
L2 L3 : L3 L4 Config
x
x
0
0
Inputs Disabled
–
x
x
0
1
High Level Sensitive
x
x
1
0
Low Level Sensitive
x
x
1
1
Both Level Sensitive
0
0
x
x
–
Inputs Disabled
0
1
x
x
High Level Sensitive
1
0
x
x
Low Level Sensitive
1
1
x
x
Both Level Sensitive
x = Don’t care.
Table 29. Wake-Up Register Status Bits
(59)
Name
Logic
Description
L3WU
0 or 1
If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has
occurred.
When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW
or HIGH) (0 = Lx LOW, 1 = Lx HIGH)
L2WU
0 or 1
L1WU
0 or 1
L0WU
0 or 1
Notes
59.
WUR status bits have two functions. After SBC wake-up, they indicate the wake up source; for example, L2WU set at logic [1] if wake-
up source is L2 input. After SBC wake-up and once the WUR register
has been read, status bits indicate the real-time state of the Lx
inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog tomato occurs before the
first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.
Table 30. TIM1 Timing and CANL Failure Diagnostic Register
TIM1
R/W
D3
D2
D1
D0
$101b
W
0
WDW
WDT1
WDT0
R
CANL2VDD
CANL2BAT
CANL2GND
TXPD
Reset Value
–
–
0
0
0
Reset Condition
(Write)
(60)
–
–
POR, RESET
POR, RESET
POR, RESET
Notes
60.
See
Table 13
, page
42
, for definitions of reset conditions.
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| MCZ33742SEGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33780EG | 功能描述:多路器開(kāi)關(guān) IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開(kāi)關(guān)數(shù)量:4 開(kāi)啟電阻（最大值）:7 Ohms 開(kāi)啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MCZ33780EG | 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC |
| MCZ33780EGR2 | 功能描述:多路器開(kāi)關(guān) IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開(kāi)關(guān)數(shù)量:4 開(kāi)啟電阻（最大值）:7 Ohms 開(kāi)啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MCZ33781EK | 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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