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參數(shù)資料
| 型號(hào)： | MCP795W22T-I/SL |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTCC 2KB EE WD/EVENT 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)，EEPROM，閏年，方波輸出，SRAM，唯一 ID，看門狗定時(shí)器 |
| 存儲(chǔ)容量： | 64B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
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2010 Microchip Technology Inc.
DS22250A-page 27
MCP4902/4912/4922
6.0
TYPICAL APPLICATIONS
The MCP4902/4912/4922 family of devices are gen-
eral purpose DACs intended to be used in applications
where a precision with low-power and moderate
bandwidth is required.
Applications generally suited for the devices are:
Set Point or Offset Trimming
Sensor Calibration
Digitally-Controlled Multiplier/Divider
Portable Instrumentation (Battery Powered)
Motor Control Feedback Loop
6.1
Digital Interface
The MCP4902/4912/4922 utilizes a 3-wire synchro-
nous serial protocol to transfer the DAC’s setup and
output values from the digital source. The serial proto-
col can be interfaced to SPI or Microwire peripherals
that is common on many microcontroller units (MCUs),
including Microchip’s PIC MCUs and dsPIC DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the two DAC
outputs. By bringing down the LDAC pin to “l(fā)ow”, all
DAC input codes and settings in the two DAC input
registers are latched into their DAC output registers at
the same time. Therefore, both DACA and DACB
outputs are updated at the same time. Figure 6-1
shows an example of the pin connections. Note that the
LDAC pin can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16-clock transmission has been received and CS pin
has been raised.
6.2
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply’s traces from various
events such as digital switching or as a result of
changes on the DAC’s output. The bypass capacitor
helps to minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy. In
this example, two bypass capacitors are used in
parallel: (a) 0.1 F (ceramic) and (b) 10 F (tantalum).
These capacitors should be placed as close to the
device power pin (VDD) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 6-1:
Typical Connection
Diagram.
6.3
Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the input and output signal
integrity, and potentially reduce the device perfor-
mance. Careful board layout will minimize these effects
and increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
VDD
AVSS
VSS
VREFA
VOUTA
VREFB
VOUTB
PIC
M
icroc
ontrol
ler
VREFA
VOUTA
VREFB
VOUTB
SDI
CS1
SDO
SCK
LDAC
CS0
C1
C2
MC
P4
9x2
MC
P
4
9x
2
C1
C1 = 10 F
C2 = 0.1 F
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