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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCP7940MT-I/MS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/19闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTCC I2C 64B SRAM 8-MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 椤炲瀷锛� | 鏅�(sh铆)閻�/鏃ユ |
| 鐗归粸(di菐n)锛� | 璀﹀牨(b脿o)鍣�锛岄枏骞达紝鏂规尝杓稿嚭锛孲RAM |
| 瀛樺劜(ch菙)瀹归噺锛� | 64B |
| 鏅�(sh铆)闁撴牸寮忥細 | HH:MM:SS锛�12/24 灏忔檪(sh铆)锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�鐣�(d膩ng)鍓嶇5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�
Micrel, Inc.
SY69754AL
August 2007
13
M9999-082107-E
hbwhelp@micrel.com or (408) 955-1690
Appendix A
Layout and General Suggestions
1.
Establish controlled impedance stripline, microstrip, or
coplanar construction techniques.
2.
Signal paths should have approximately the same width
as the device pads.
3.
All differential paths are critical timing paths, where
skew should be matched to within 卤10ps.
4.
Signal trace impedance should not vary more than
卤5%. If in doubt, perform TDR analysis of all high-speed
signal traces.
5.
Maintain compact filter networks as close to filter pins
as possible. Provide ground plane relief under filter path
to reduce stray capacitance. Be careful of crosstalk
coupling into the filter network.
6.
Maintain low jitter on the REFCLK input. Isolate the
XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and
minimize capacitive coupling from adjacent signals.
7.
Higher speed operation may require use of
fundamental-tone (third-overtone typically has more
jitter) crystal-based oscillator for optimum performance.
Evaluate and compare candidates by measuring
TXCLK jitter.
8.
All unused outputs require termination. To conserve
power, unused PECL outputs can be terminated with a
1k resistor to VEE.
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