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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCP7940M-I/ST |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 17/19闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTCC 64B I2C SRAM 8-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 椤炲瀷锛� | 鏅�(sh铆)閻�/鏃ユ |
| 鐗归粸(di菐n)锛� | 璀﹀牨(b脿o)鍣�锛岄枏骞�锛屾柟娉㈣几鍑�锛孲RAM |
| 瀛樺劜(ch菙)瀹归噺锛� | 64B |
| 鏅�(sh铆)闁撴牸寮忥細 | HH:MM:SS锛�12/24 灏忔檪(sh铆)锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-TSSOP |
| 鍖呰锛� | 绠′欢 |
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2012 Microchip Technology Inc.
Preliminary
DS22292A-page 7
MCP7940M
3.0
I2C BUS CHARACTERISTICS
3.1
I2C Interface
The MCP7940M supports a bidirectional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the Start
and Stop conditions, while the MCP7940M works as
slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
3.1.1
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1.1.1
Bus not Busy (A)
Both data and clock lines remain high.
3.1.1.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.1.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
3.1.1.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
3.1.1.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (MCP7940M) will leave the data line high to
enable the master to generate the Stop condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A)
(B)
(D)
(C)
(A)
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