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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCP6V26-E/MS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/50闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP AUTO-ZERO SGL 8MSOP |
| 妯欐簴鍖呰锛� | 100 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 鑷嫊瑾�(di脿o)闆� |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杓稿嚭椤炲瀷锛� | 婊挎摵骞� |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 1 V/µs |
| 澧炵泭甯跺绌嶏細 | 2MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 7pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 2µV |
| 闆绘祦 - 闆绘簮锛� | 620µA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 22mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 2.3 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
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MCP6V26/7/8
DS25007B-page 24
2011 Microchip Technology Inc.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN鈥�) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
4.2.2
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V26/7/8
zero-drift op amps is VDD 鈥� 15 mV (minimum) and
VSS + 15 mV (maximum) when RL =10 k惟 is
connected to VDD/2 and VDD = 5.5V. Refer to
Figure 2-19 and Figure 2-20.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.2.3
CHIP SELECT (CS)
The single MCP6V28 has a Chip Select (CS) pin.
When CS is pulled high, the supply current for the
corresponding op amp drops to about 1 A (typical),
and is pulled through the CS pin to VSS. When this
happens, the amplifier is put into a high impedance
state. By pulling CS low, the amplifier is enabled. If the
CS pin is left floating, the internal pull-down resistor
(about 5 M
惟) will keep the part on. Figure 1-4 shows
the output voltage and supply current response to a CS
pulse.
4.3
Application Tips
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2
DC GAIN PLOTS
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms
of the reciprocals (in units of V/V) of CMRR, PSRR
and AOL, respectively. They represent the change in
input offset voltage (VOS) with a change in common
mode input voltage (VCM), power supply voltage (VDD)
and output voltage (VOUT).
The 1/AOL histogram is centered near 0 V/V because
the measurements are dominated by the op amp鈥檚
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps鈥�
stability by making multiple measurements of VOS; an
unstable part would fail, because it would show either
greater variability in VOS, or the output stuck at one of
the rails.
4.3.3
OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
卤5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the startup time (like
tSTR).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
4.3.4
SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85掳C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10
惟
to 1 k
惟 at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances are needed for high gains.
Without them, parasitic capacitances can cause
positive feedback and instability.
4.3.5
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.
V
OS TA
()
V
OS
TC
1螖TTC2螖T
2
++
=
Where:
螖T=
TA 鈥�25掳C
VOS(TA)
=
input offset voltage at TA
VOS
=
input offset voltage at +25掳C
TC1
=
linear temperature coefficient
TC2
=
quadratic temperature
coefficient
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| MCP6V26T-E/MNY | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 Single, Auto-Zero Op Amp, E Temp RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| MCP6V26T-E/MS | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 Single, Auto-Zero Op Amp, E Temp RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| MCP6V26T-E/SN | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 Single, Auto-Zero Op Amp, E Temp RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| MCP6V27-E/MD | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 620 uA, 2 MHz Auto-Zeroed Op Amps RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞�(zhu菐n)鎻涢€熷害:0.89 V/us 闂�(gu膩n)闁�:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| MCP6V27-E/MD | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:; Peak Reflow Compatible (260 C):Yes; Le |
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