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| 型號： | MCP631T-E/MNY |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP SGL 24MHZ 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 10 V/µs |
| 增益帶寬積： | 24MHz |
| 電流 - 輸入偏壓： | 4pA |
| 電壓 - 輸入偏移： | 1800µV |
| 電流 - 電源： | 2.5mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（2x3） |
| 包裝： | 帶卷 (TR) |
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2009-2011 Microchip Technology Inc.
DS22197B-page 21
MCP631/2/3/4/5/9
4.0
APPLICATIONS
The MCP631/2/3/4/5/9 family op amps is manufactured
using the Microchip state-of-the-art CMOS process. It
is designed for low cost, low power and high speed
applications. Its low supply voltage, low quiescent
current and wide bandwidth make the MCP631/2/3/4/5/
9 ideal for battery-powered applications.
4.1
Input
4.1.1
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.
Figure 2-38 shows
an
input voltage
exceeding both supplies with no phase inversion.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The electrostatic discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors,
and to minimize input bias current (IB). The input ESD
diodes clamp the inputs when they try to go more than
one diode drop below VSS. They also clamp any volt-
ages that go too far above VDD; their breakdown volt-
age is high enough to allow normal operation, and low
enough to bypass quick ESD events within the speci-
fied limits.
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins
(VIN+and VIN-) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN-) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush
current limiters; the DC current into the input pins
(VIN+ and VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-13. Applications that are high-impedance may
need to limit the usable voltage range.
4.1.3
NORMAL OPERATION
The input stage of the MCP631/2/3/4/5/9 op amps uses
a differential PMOS input stage. It operates at
low common mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured
at both
VCM =VSS – 0.3V
and
VDD –1.3V.
See Figure 2-5 and Figure 2-6 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
FIGURE 4-3:
Unity Gain Voltage
Limitations for Linear Operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN-
V1
R1
VDD
D1
R1 >
VSS – (minimum expected V1)
2mA
VOUT
R2 >
VSS – (minimum expected V2)
2mA
V2
R2
D2
MCP63X
VIN
VDD
VOUT
VSS V
IN V
OUT
VDD 1.3V
–
MCP63X
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