參數(shù)資料
型號： MCP6284
廠商： Microchip Technology Inc.
英文描述： 450 UA, 5 MHz Rail-to-Rail Op Amp
中文描述： 450聯(lián)合航空表示，5兆赫軌到軌運算放大器
文件頁數(shù)： 11/32頁
文件大小： 580K
代理商： MCP6284
2004 Microchip Technology Inc.
DS21811D-page 11
MCP6281/2/3/4/5
4.0
APPLICATION INFORMATION
The MCP6281/2/3/4/5 family of op amps is manufac-
tured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low-
cost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/2/3/4/5 ideal for
battery-powered applications.
4.1
Rail-to-Rail Inputs
The MCP6281/2/3/4/5 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
FIGURE 4-1:
No Phase Reversal.
The MCP6281/2/3/4/5 Show
The input stage of the MCP6281/2/3/4/5 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
),
while the other operates at high V
CM
. With this
topology, the device operates with V
CM
up to 0.3V
above V
DD
and 0.3V below V
SS
. The Input Offset Volt-
age (V
OS
) is measured at V
CM
= V
SS
– 0.3V and
V
DD
+ 0.3V to ensure proper operation.
Input voltages that exceed the absolute maximum
voltage (V
SS
– 0.3V to V
DD
+ 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
FIGURE 4-2:
Resistor (R
IN
).
Input Current Limiting
4.2
Rail-to-Rail Output
The output voltage range of the MCP6281/2/3/4/5 op
amp is V
DD
– 15 mV (min.) and V
SS
+ 15 mV (max.)
when R
L
= 10 k
is connected to V
DD
/2 and
V
DD
= 5.5V. Refer to Figure 2-16 for more information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
FIGURE 4-3:
stabilizes large capacitive loads.
Output Resistor, R
ISO
Figure 4-4 gives recommended R
ISO
values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
-1
0
1
2
3
4
5
6
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
Time (1 ms/div)
I
V
DD
= 5.0V
G = +2 V/V
V
IN
V
OUT
RIN
VSS
Minimum expected VIN
2 mA
(
)
–
≥
RIN
-Maximum expected VIN
(
)
VDD
–
2 mA
≥
V
IN
R
IN
V
OUT
–
+
MCP628X
V
IN
R
ISO
V
OUT
C
L
–
MCP628X
+
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