參數(shù)資料
型號: MCP6273
廠商: Microchip Technology Inc.
元件分類: FPGA
英文描述: 300000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 170聯(lián)合航空表示,2 MHz的軌到軌運算放大器
文件頁數(shù): 14/34頁
文件大?。?/td> 596K
代理商: MCP6273
MCP6271/2/3/4/5
DS21810D-page 14
2004 Microchip Technology Inc.
4.8.2
LOSSY NON-INVERTING
INTEGRATOR
The non-inverting integrator shown in Figure 4-8 is easy
to build. It saves one op amp over the typical Miller
integrator plus inverting amplifier configuration. The
phase accuracy of this integrator depends on the
matching of the input and feedback resistors, and the
capacitor’s time constants. R
F
is used to provide
feedback at frequencies << 1/(2
π
R
1
C
1
) and makes this
a lossy integrator (it has infinite gain at DC).
FIGURE 4-8:
Non-Inverting Integrator.
4.8.3
CASCADED OP AMP
APPLICATIONS
The MCP6275 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery-powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
4.8.3.1
Load Isolation
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions where op amp A is driving capacitive or low resis-
tive loads in the feedback loop (such as an integrator or
filter circuit) the op amp may not have sufficient source
current to drive the load. In this case, op amp B can be
used as a buffer.
FIGURE 4-9:
Buffer.
Isolating the Load with a
4.8.3.2
Figure 4-10 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this config-
uration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
Cascaded Gain
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity-gain buffer).
+
MCP6271
_
C
1
C
2
R
1
R
2
V
IN
V
OUT
R
F
R
1
C
1
R
2
R
F
||
(
)
C
2
=
A
B
MCP6275
CS
V
OUTB
Load
V
OUT
V
IN
G
A
G
B
V
OSA
G
A
G
B
V
OSB
G
B
+
+
=
Where:
G
A
= op amp A gain
G
B
= op amp B gain
V
OSA
= op amp A input offset voltage
V
OSB
= op amp B input offset voltage
相關(guān)PDF資料
PDF描述
MCP6274 300,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
MCP6275 170 UA, 2 MHz Rail-to-Rail Op Amp
MCP6291 1.0 mA, 10 MHz Rail-to-Rail Op Amp
MCP6292T 1.0 mA, 10 MHz Rail-to-Rail Op Amp
MCP6293 1.0 mA, 10 MHz Rail-to-Rail Op Amp
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MCP6273-E/P 功能描述:運算放大器 - 運放 Single 2MHz RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比(最小值):63 dB 輸入補償電壓:1 mV 輸入偏流(最大值):10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
MCP6273-E/SN 功能描述:運算放大器 - 運放 Single 2MHz RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比(最小值):63 dB 輸入補償電壓:1 mV 輸入偏流(最大值):10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
MCP6273T-E/CH 功能描述:運算放大器 - 運放 Single 2 MHz OP w/ CS E temp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比(最小值):63 dB 輸入補償電壓:1 mV 輸入偏流(最大值):10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
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