參數資料
型號： MCP621T-E/MNY
廠商： Microchip Technology
文件頁數： 18/66頁
文件大?。?/td> 0K
描述： IC OPAMP SGL 20MHZ 8TDFN
標準包裝： 3,300
系列： mCal 技術
放大器類型： 通用
電路數： 1
輸出類型： 滿擺幅
轉換速率： 10 V/µs
增益帶寬積： 20MHz
電流 - 輸入偏壓： 5pA
電壓 - 輸入偏移： 200µV
電流 - 電源： 2.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤
供應商設備封裝： 8-TDFN（2x3）
包裝： 帶卷 (TR)
2009-2011 Microchip Technology Inc.
DS22188C-page 25
MCP621/1S/2/3/4/5/9
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (VCM) is below ground (VSS); see
Figure 2-15. Applications that are high-impedance may
need to limit the usable voltage range.
4.2.3
NORMAL OPERATION
The input stage of the MCP621/1S/2/3/4/5/9 op amps
use a differential PMOS input stage. It operates at low
Common mode input voltage (VCM), with VCM up to
VDD – 1.3V and down to VSS – 0.3V. The input offset
voltage (VOS) is measured at VCM =VSS –0.3V and
VDD – 1.3V to ensure proper operation. See Figure 2-6
and Figure 2-7 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD –1.3V); see Figure 4-5.
FIGURE 4-5:
Unity Gain Voltage
Limitations for Linear Operation.
4.3
Rail-to-Rail Output
4.3.1
MAXIMUM OUTPUT VOLTAGE
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
40 mV of the negative rail with a 2 k
Ω load tied to
VDD/2.
4.3.2
OUTPUT CURRENT
Figure 4-6 shows the possible combinations of output
voltage (VOUT) and output current (IOUT). IOUT is
positive when it flows out of the op amp into the
external circuit.
FIGURE 4-6:
Output Current.
4.3.2.1
Power Dissipation
Since the output short circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering
and
dissipating
significant
power.
Two common loads, and their impact on the op amp’s
power dissipation, will be discussed.
Figure 4-7 shows a resistive load (RL) with a DC output
voltage (VOUT). VL is RL’s ground point, VSS is usually
ground (0V) and IOUT is the output current. The input
currents are assumed to be negligible.
FIGURE 4-7:
Diagram for Resistive Load
Power Calculations.
The DC currents are:
EQUATION 4-1:
The DC op amp power is:
EQUATION 4-2:
The maximum op amp power, for resistive loads at DC,
occurs when VOUT is halfway between VDD and VL, or
halfway between VSS and VL:
EQUATION 4-3:
VIN
VDD
VOUT
V
SS
V
<
IN
V
,
OUT
V
DD
1.3V
–
≤
MCP62X
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-8
0
-6
0
-4
0
-2
0
20
40
60
80
IOUT (mA)
V
OU
T(V
)
RL = 10
RL = 100
RL = 2 k
VOH Limited
VOL Limited
-I
SC
Li
m
ite
d
+I
SC
L
im
ite
d
(VDD = 5.5V)
VDD
VOUT
RL
VL
IDD
ISS
IOUT
VSS
MCP62X
I
OUT
V
OUT
V
L
–
R
L
--------------------------
=
I
DD
I
Q
max 0 I
OUT
,
()
+
≈
I
SS
I
–
Q
min 0 I
OUT
,
()
+
≈
Where:
IQ = Quiescent supply current for one op
amp (mA/amplifier)
VOUT = A DC value (V)
P
OA
I
DD VDD
V
OUT
–
() I
SS VSS
V
OUT
–
()
+
=
max P
OA
()
I
DD VDD
V
SS
–
()
=
max
2
V
DD
V
L
–
V
L
V
SS
–
,
()
4R
L
------------------------------------------------------------------
+
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