參數(shù)資料
型號(hào)： MCP47DA1T-A0E/OT
廠商： Microchip Technology
文件頁(yè)數(shù)： 20/54頁(yè)
文件大小： 0K
描述： IC DGTL POT 30K 1CH SOT-23-6
標(biāo)準(zhǔn)包裝： 1
接片： 65
電阻（歐姆）： 30k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C
電源電壓： 1.8 V ~ 5.5 V，2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： MCP47DA1T-A0E/OTDKR
Micrel, Inc.
KSZ8041NL/RNL
September 2010
27
M9999-090910-1.4
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
RMII Signal Diagram
The KSZ8041NL RMII pin connections to the MAC are shown in Figure 2.
Figure 2. KSZ8041NL RMII Interface
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