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參數(shù)資料
| 型號： | MCP4728T-E/UN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 28/33頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT W/I2C 10-MSOP |
| 視頻文件： | MCP4728 Evaluation Board Demo |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 配用： | MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728 |
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MCP4728
DS22187E-page 4
2010 Microchip Technology Inc.
Power-on Reset
Threshold Voltage
VPOR
—
2.2
—
V
All circuits, including EEPROM, are
ready to operate.
Power-Up Ramp Rate
VRAMP
1—
—
V/s
DC Accuracy
Resolution
n
12
—
Bits
Code Change: 000h to FFFh
Integral Nonlinearity (INL)
Error
INL
—
±2
±13
LSB
DNL Error
DNL
-0.75
±0.2
±0.75
LSB
Offset Error
VOS
—
5
20
mV
Code = 000h
See Figure 2-24
Offset Error Drift
ΔV
OS/°C
—
±0.16
—
ppm/°C -45°C to +25°C
—
±0.44
—
ppm/°C +25°C to +125°C
Gain Error
GE
-1.25
0.4
+1.25
% of
FSR
Code = FFFh,
Offset error is not included.
Typical value is at room
temperature
See Figure 2-25
Gain Error Drift
ΔG
E/°C
—
-3
—
ppm/°C
Internal Voltage Reference
VREF
2.007
2.048
2.089
V
Temperature Coefficient
ΔV
REF/°C
—
125
—
ppm/°C
-40 to 0°C
—
0.25
—
LSB/°C
—
45
—
ppm/°C
0 to +125°C
—
0.09
—
LSB/°C
Reference Output Noise
ENREF
—
290
—
Vp-p
Code = FFFh,
0.1 – 10 Hz, Gx =1
Output Noise Density
eNREF
—
1.2
—
Code = FFFh, 1 kHz, Gx =1
—
1.0
—
Code = FFFh, 10 kHz, Gx =1
1/f Corner Frequency
fCORNER
—
400
—
Hz
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at V
DD = +2.7V to 5.5V, VSS =0V,
RL =5 kΩ, CL = 100 pF, GX =1, TA = -40°C to +125°C. Typical values are at +25°C, VIH =VDD, VIL =VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Note 1:
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
2:
The power-up ramp rate measures the rise of VDD over time.
3:
This parameter is ensured by design and not 100% tested.
4:
This parameter is ensured by characterization and not 100% tested.
5:
Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6:
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7:
This parameter is indirectly tested by Offset and Gain error testing.
8:
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9:
This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.
This time delay is not included in the output settling time specification.
HZ
μV
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