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參數資料
| 型號： | MCP4726A2T-E/CH |
| 廠商： | Microchip Technology |
| 文件頁數： | 42/86頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C SOT-23-6 |
| 標準包裝： | 3,000 |
| 設置時間： | 6µs |
| 位數： | 12 |
| 數據接口： | EEPROM，I²C，串行 |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 452mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
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2011-2012 Microchip Technology Inc.
DS22272C-page 47
MCP4706/4716/4726
5.3.6
HS MODE
The I2C specification requires that a High-Speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the master sending
a special address byte following the Start bit. This byte
is referred to as the High-Speed Master Mode Code
(HSMMC).
The MCP47X6 device does not acknowledge this byte.
However, upon receiving this command, the device
switches
to
HS
mode.
The
device
can
now
communicate at up to 3.4 Mbit/s on SDA and SCL
lines. The device will switch out of the HS mode on the
next Stop condition.
The master code is sent as follows:
1.
Start condition (S)
2.
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the High-Speed (HS)
mode master.
3.
No Acknowledge (A)
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The master device
can then either issue a Repeated Start bit to address a
different device (at High-Speed) or a Stop bit to return
to Fast/Standard bus speed. After the Stop bit, any
other master device (in a multi-master system) can
arbitrate for the I2C bus.
See Figure 5-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the NXP I2C specification.
5.3.6.1
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
5.3.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 5-10:
HS Mode Sequence.
S
A
‘0 0 0 0 1 X X X’b
Sr
A
‘Slave Address’
A/A
“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS mode)
F/S-mode
HS mode
HS mode continues
F/S mode
Sr
A
‘Slave Address’ R/W
HS Select Byte
Control Byte
Command/Data Byte(s)
Control Byte
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