參數(shù)資料
      型號(hào): MCP4726A0T-E/MAY
      廠商: Microchip Technology
      文件頁(yè)數(shù): 40/86頁(yè)
      文件大?。?/td> 0K
      描述: IC DAC 12BIT NV EEP I2C 6DFN
      標(biāo)準(zhǔn)包裝: 1
      設(shè)置時(shí)間: 6µs
      位數(shù): 12
      數(shù)據(jù)接口: EEPROM,I²C,串行
      轉(zhuǎn)換器數(shù)目: 1
      電壓電源: 單電源
      功率耗散(最大): 1.10W
      工作溫度: -40°C ~ 125°C
      安裝類型: 表面貼裝
      封裝/外殼: 6-VDFN 裸露焊盤
      供應(yīng)商設(shè)備封裝: 6-DFN(2x2)
      包裝: 標(biāo)準(zhǔn)包裝
      輸出數(shù)目和類型: 1 電壓,單極
      采樣率(每秒): *
      其它名稱: MCP4726A0T-E/MAYDKR
      2011-2012 Microchip Technology Inc.
      DS22272C-page 45
      MCP4706/4716/4726
      5.3.1.4
      Repeated Start Bit
      The Repeated Start bit (see Figure 5-5) indicates the
      current
      master
      device
      wishes
      to
      continue
      communicating with the current slave device without
      releasing the I2C bus. The Repeated Start condition is
      the same as the Start condition, except that the
      Repeated Start bit follows a Start bit (with the Data bits
      + A bit) and not a Stop bit.
      The Start bit is the beginning of a data transfer
      sequence and is defined as the SDA signal falling when
      the SCL signal is “High”.
      FIGURE 5-5:
      Repeat Start Condition
      Waveform.
      5.3.1.5
      Stop Bit
      The Stop bit (see Figure 5-6) Indicates the end of the
      I2C Data Transfer Sequence. The Stop bit is defined as
      the SDA signal rising when the SCL signal is “High”.
      A Stop bit resets the I2C interface of all MCP47X6
      devices.
      FIGURE 5-6:
      Stop Condition Receive or
      Transmit Mode.
      5.3.2
      CLOCK STRETCHING
      “Clock Stretching” is something that the receiving
      Device can do, to allow additional time to “respond” to
      the “data” that has been received.
      The MCP47X6 will not stretch the clock signal (SCL)
      since memory read access occurs fast enough.
      5.3.3
      ABORTING A TRANSMISSION
      If any part of the I2C transmission does not meet the
      command format, it is aborted. This can be intentionally
      accomplished with a Start or Stop condition. This is
      done so that noisy transmissions (usually an extra Start
      or Stop condition) are aborted before they corrupt the
      device.
      FIGURE 5-7:
      Typical 8-Bit I2C Waveform Format.
      FIGURE 5-8:
      I2C Data States and Bit Sequence.
      Note 1: A bus collision during the Repeated Start
      condition occurs if:
      SDA is sampled low when SCL goes
      from low to high.
      SCL goes low before SDA is asserted
      low. This may indicate that another
      master is attempting to transmit a
      data "1".
      SDA
      SCL
      Sr = Repeated Start
      1st Bit
      SCL
      SDA A / A
      P
      1st Bit
      SDA
      SCL
      S
      2nd Bit
      3rd Bit
      4th Bit
      5th Bit
      6th Bit
      7th Bit
      8th Bit
      P
      A / A
      SCL
      SDA
      Start
      Condition
      Stop
      Condition
      Data allowed
      to change
      Data or
      A valid
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