- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17108 > MCP4725DM-PTPLS (Microchip Technology)BOARD DAUGHTER PICTAIL MCP4725 PDF資料下載
參數(shù)資料
| 型號(hào)： | MCP4725DM-PTPLS |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 8/50頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAUGHTER PICTAIL MCP4725 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k ~ 3.4M |
| 數(shù)據(jù)接口： | I²C |
| 設(shè)置時(shí)間： | 6µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | MCP4725 |
| 產(chǎn)品目錄頁(yè)面： | 673 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | MCP4725A3T-E/CHDKR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A2T-E/CHDKR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A1T-E/CHDKR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A3T-E/CHCT-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A2T-E/CHCT-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A1T-E/CHCT-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A3T-E/CHTR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A2T-E/CHTR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A1T-E/CHTR-ND - IC DAC 12BIT EE W/I2C SOT23-6 MCP4725A0T-E/CHTR-ND - IC DAC 12BIT W/I2C SOT23A-6 更多... |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)
MCP4725
DS22039D-page 16
2009 Microchip Technology Inc.
FIGURE 4-2:
DNL Accuracy.
4.5
Offset Error
Offset error (Figure 4-3) is the deviation from zero volt-
age output when the digital input code is zero. This
error affects all codes by the same amount. In the
MCP4725, the offset error is not trimmed at the factory.
However, it can be calibrated by software in application
circuits.
FIGURE 4-3:
Offset Error.
4.6
Gain Error
Gain error (see Figure 4-4) is the difference between
the actual full scale output voltage from the ideal output
voltage on the transfer curve. The gain error is
calculated after nullifying the offset error, or full scale
error minus the offset error.
The gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. The gain error is usually expressed as percent
of full scale range (% of FSR) or in LSB.
In the MCP4725, the gain error is not calibrated at the
factory and most of the gain error is contributed by the
output op amp saturation near the code range beyond
4000. For the applications which need the gain error
specification less than 1% maximum, the user may
consider using the DAC code range between 100 and
4000 instead of using full code range (code 0 to 4095).
The DAC output of the code range between 100 and
4000 is much linear than full scale range (0 to 4095).
The gain error can be calibrated by software in
applications.
4.7
Full Scale Error (FSE)
Full scale error (Figure 4-4) is the sum of offset error
plus gain error. It is the difference between the ideal
and measured DAC output voltage with all bits set to
one (DAC input code = FFFh).
EQUATION 4-4:
FIGURE 4-4:
Gain Error and Full Scale
Error.
4.8
Gain Error Drift
Gain error drift is the variation in gain error due to a
change in ambient temperature. The gain error drift is
typically expressed in ppm/oC.
010
001
000
Analog
Output
(LSB)
DAC Input Code
011
111
100 101
1
2
3
4
5
6
0
7
DNL = 2LSB
DNL = 0.5 LSB
110
Ideal Transfer Function
Actual Transfer Function
Analog
Output
Ideal Transfer Function
Actual Transfer Function
DAC Input Code
0
Offset
Error
FSE
V
OUT
V
Ideal
–
()
LSB
---------------------------------------
=
Where:
VIdeal
=(VREF) (1 - 2-n) - VOFFSET
VREF
=
The reference voltage.
VREF = VDD in the MCP4725
Analog
Output
Actual Transfer Function
DAC Input Code
0
Gain Error
Ideal Transfer Function
after Offset Error Removed
Full Scale
Error
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EEM36DTBD-S189 | CONN EDGECARD 72POS R/A .156 SLD |
| 9410990001 | HEAT SHRINK SLEEVE |
| EEM36DSEI | CONN EDGECARD 72POS .156 EYELET |
| SCRH4D18-4R7 | INDUCTOR SMD 4.7UH 0.84A 100KHZ |
| EEM36DTAN-S189 | CONN EDGECARD 72POS R/A .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCP4725EV | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MCP4725 Eval Brd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MCP4725T-E/CH | 功能描述:數(shù)模轉(zhuǎn)換器- DAC SNGL 12B NV DAC with I2C interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MCP4726A0T-E/CH | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Sngl 12B NV DAC w/Ex Vref & I2C interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MCP4726A0T-E/MAY | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Sngl 12B NV DAC w/Ex Vref & I2C interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MCP4726A1T-E/CH | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Sngl 12B NV DAC w/Ex Vref & I2C interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。