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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCP4652T-503E/UN |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 6/88闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC POT DGTL 50K DUAL 10-MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鎺ョ墖锛� | 257 |
| 闆婚樆锛堟瓙濮嗭級锛� | 50k |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 150 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | I²C锛堣ō(sh猫)鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-MSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
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MCP453X/455X/463X/465X
DS22096A-page 14
2008 Microchip Technology Inc.
FIGURE 1-2:
I2C Bus Data Timing.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
TABLE 1-2:
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
鈥�40
掳C 鈮� TA 鈮� +125掳C (Extended)
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4000
鈥�
ns
1.8V-5.5V
400 kHz mode
600
鈥�
ns
2.7V-5.5V
1.7 MHz mode
120
ns
4.5V-5.5V
3.4 MHz mode
60
鈥�
ns
4.5V-5.5V
101
TLOW
Clock low time
100 kHz mode
4700
鈥�
ns
1.8V-5.5V
400 kHz mode
1300
鈥�
ns
2.7V-5.5V
1.7 MHz mode
320
ns
4.5V-5.5V
3.4 MHz mode
160
鈥�
ns
4.5V-5.5V
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 鈮� 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
2C bus specification) before
the SCL line is released.
3:
The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I
2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4:
Use Cb in pF for the calculations.
5:
Not Tested
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7:
Ensured by the TAA 3.4 MHz specification test.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-2N1-MY-F3 | CONVERTER MOD DC/DC 12V 50W |
| VI-2N1-MY-F2 | CONVERTER MOD DC/DC 12V 50W |
| MCP4652T-104E/UN | IC POT DGTL 100K DUAL 10-MSOP |
| VI-2N0-MY-F4 | CONVERTER MOD DC/DC 5V 50W |
| VI-2N0-MY-F3 | CONVERTER MOD DC/DC 5V 50W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MCP4661-103E/ST | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓(j矛) IC Sngl 8B NV I2C POT RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜(ch菙)鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4661-104E/ST | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓(j矛) IC Sngl 8B NV I2C POT RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜(ch菙)鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4661-104E/ST | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MCP4661-502E/ST | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓(j矛) IC Sngl 8B NV I2C POT RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜(ch菙)鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4661-502E/ST | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
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