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鍙冩暩璩囨枡
鍨嬭櫉锛� MCP4532T-104E/MS
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩锛� 6/88闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC POT DGTL 100K SGL 8-MSOP
妯欐簴鍖呰锛� 2,500
鎺ョ墖锛� 129
闆婚樆锛堟瓙濮嗭級锛� 100k
闆昏矾鏁革細 1
婧害绯绘暩锛� 妯欐簴鍊� 150 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 鏄撳け
鎺ュ彛锛� I²C锛堣ō鍌欎綅鍧€锛�
闆绘簮闆诲锛� 1.8 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-MSOP
鍖呰锛� 甯跺嵎 (TR)
MCP453X/455X/463X/465X
DS22096A-page 14
2008 Microchip Technology Inc.
FIGURE 1-2:
I2C Bus Data Timing.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
TABLE 1-2:
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
鈥�40
掳C 鈮� TA 鈮� +125掳C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4000
鈥�
ns
1.8V-5.5V
400 kHz mode
600
鈥�
ns
2.7V-5.5V
1.7 MHz mode
120
ns
4.5V-5.5V
3.4 MHz mode
60
鈥�
ns
4.5V-5.5V
101
TLOW
Clock low time
100 kHz mode
4700
鈥�
ns
1.8V-5.5V
400 kHz mode
1300
鈥�
ns
2.7V-5.5V
1.7 MHz mode
320
ns
4.5V-5.5V
3.4 MHz mode
160
鈥�
ns
4.5V-5.5V
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 鈮� 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
2C bus specification) before
the SCL line is released.
3:
The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I
2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4:
Use Cb in pF for the calculations.
5:
Not Tested
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7:
Ensured by the TAA 3.4 MHz specification test.
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