- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9353 > MCP4531T-503E/MS (Microchip Technology)IC POT DGTL 50K SGL 8-MSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCP4531T-503E/MS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 41/88闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC POT DGTL 50K SGL 8-MSOP |
| 妯欐簴鍖呰锛� | 2,500 |
| 鎺ョ墖锛� | 129 |
| 闆婚樆锛堟瓙濮嗭級锛� | 50k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯欐簴鍊� 150 ppm/°C |
| 瀛樺劜鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | I²C锛堣ō鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�鐣跺墠绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�
MCP453X/455X/463X/465X
DS22096A-page 46
2008 Microchip Technology Inc.
6.2
I2C Operation
The MCP45XX/46XX鈥檚 I2C module is compatible with
the Philips I2C specification. The following lists some of
the modules features:
7-bit slave addressing
Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
Support Multi-Master Applications
General call addressing
Internal weak pull-ups on interface signals
The I2C 10-bit addressing mode is not supported.
The Philips I2C specification only defines the field
types, field lengths, timings, etc. of a frame. The frame
content defines the behavior of the device. The frame
content for the MCP4XXX is defined in Section 7.0.
6.2.1
I2C BIT STATES AND SEQUENCE
clock is generated by the master. The following defini-
tions are used for the bit states:
Start bit (S)
Data bit
Acknowledge (A) bit (driven low) /
No Acknowledge (A) bit (not driven low)
Repeated Start bit (Sr)
Stop bit (P)
6.2.1.1
Start Bit
The Start bit (see Figure 6-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is 鈥淗igh鈥�.
FIGURE 6-2:
Start Bit.
6.2.1.2
Data Bit
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 6-5).
FIGURE 6-3:
Data Bit.
6.2.1.3
Acknowledge (A) Bit
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically the Slave
device will supply an A response after the Start bit and
8 鈥渄ata鈥� bits have been received. an A bit has the SDA
signal low.
FIGURE 6-4:
Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 6-1 shows
some of the conditions where the Slave Device will
issue a Not A (A).
If an error condition occurs (such as an A instead of A),
then an START bit must be issued to reset the
command state machine.
TABLE 6-1:
MCP45XX/MCP46XX A / A
RESPONSES
SDA
SCL
S
1st Bit
2nd Bit
SDA
SCL
Data Bit
1st Bit
2nd Bit
Event
Acknowledge
Bit
Response
Comment
General Call
A
Only if GCEN bit is
set
Slave Address
valid
A
Slave Address
not valid
A
Device Mem-
ory Address
and specified
command
(AD3:AD0 and
C1:C0) are an
invalid combi-
nation
A
After device has
received address
and command
Bus Collision
N.A.
I2C Module
Resets, or a 鈥淒on鈥檛
Care鈥� if the colli-
sion occurs on the
Masters 鈥淪tart bit鈥�.
A
8
D0
9
SDA
SCL
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MS3106E32-12S | CONN PLUG 15POS STRAIGHT W/SCKT |
| MS27472E24B35P | CONN RCPT 128POS WALL MNT W/PINS |
| D38999/20WC4SN | CONN RCPT 4POS WALL MNT W/SCKT |
| MCP4132T-503E/SN | IC RHEO DGTL SNGL 50K SPI 8SOIC |
| D38999/26WH21PC | CONN PLUG 21POS STRAIGHT W/PINS |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MCP4532-103E/MS | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓ IC Sngl 7B V I2C Rheo RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4532-104E/MS | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓ IC Sngl 7B V I2C Rheo RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4532-104E/MS | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MCP4532-502E/MS | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓ IC Sngl 7B V I2C Rheo RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| MCP4532-502E/MS | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�
