I2C Read (Last" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCP4461-502E/ST
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 65/100闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC POT 8BIT QUAD NONV 5K 20TSSOP
妯欐簴鍖呰锛� 74
鎺ョ墖锛� 257
闆婚樆锛堟瓙濮嗭級锛� 5k
闆昏矾鏁�(sh霉)锛� 4
婧害绯绘暩(sh霉)锛� 妯欐簴鍊� 150 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 闈炴槗澶�
鎺ュ彛锛� I²C锛堣ō鍌欎綅鍧€锛�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 20-TSSOP
鍖呰锛� 绠′欢
2010 Microchip Technology Inc.
DS22265A-page 67
MCP444X/446X
FIGURE 7-4:
I2C Read (Last Memory Address Accessed).
FIGURE 7-5:
I2C Random Read.
STOP bit
Control Byte
1
010
S
1 A1 A0 1 A
Fixed
Address
Variable
Address
Read bits
P
0
000
0
0 D8 A1
Read bit
D3
D7 D6 D5 D4
D2 D1 D0 A2
Read Data bits
Note 1:
Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this
transfer and release the bus.
2:
The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3:
The MCP44XX retains the last 鈥淒evice Memory Address鈥� that it has received. This is the
MCP44XX does not 鈥渃orrupt鈥� the 鈥淒evice Memory Address鈥� after Repeated Start or Stop
conditions.
4:
The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
STOP bit
Control Byte
READ Command
1
01 0
S
1 A1 A0 0
1
AD AD AD AD
A1 x X A Sr
0
1
2
3
Fixed
Address
Variable
Address
Device
Memory
Address
Command
Control Byte
Read bits
P
0
00 0
0
0 D8 A1
Write bit
D3
D7 D6 D5 D4
D2 D1 D0 A2
1
0 1 0
1 A1 A0 1
A
Read bit
Repeated Start bit
Read Data bits
Note 1:
Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this
transfer and release the bus.
2:
The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Mas-
ter Device can generate a Stop or Repeated Start condition.
3:
The MCP44XX retains the last 鈥淒evice Memory Address鈥� that it has received. This is the
MCP44XX does not 鈥渃orrupt鈥� the 鈥淒evice Memory Address鈥� after Repeated Start or Stop
conditions.
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