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| 型號： | MCP4442T-103E/ST |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 41/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 129TAPS 10K 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 129 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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2010 Microchip Technology Inc.
DS22265A-page 45
MCP444X/446X
bit 3
WL1:
WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock Technology” for
further information)
The WiperLock Technology bit (WL1) prevents the Volatile and Nonvolatile Wiper 1 addresses and the
TCON0 register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1
= Wiper and TCON0 register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are
“Locked” (Write Protected)
0
= Wiper and TCON0 of Resistor Network 1 (Pot 1) can be modified
Note:
The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1
bit. After a POR/BOR or RESET pin event, the WL1 bit is loaded with the nonvolatile WL1 bit
value.
bit 2
WL0:
WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock Technology” for
further information)
The WiperLock Technology bit (WL0) prevents the Volatile and Nonvolatile Wiper 0 addresses and the
TCON0 register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1
= Wiper and TCON0 register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are
“Locked” (Write Protected)
0
= Wiper and TCON0 of Resistor Network 0 (Pot 0) can be modified
Note:
The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0
bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the nonvolatile WL0 bit
value.
bit 1
Reserved:
Forced to “1”
bit 0
WP:
EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further
information)
This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is
enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM
memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile
wiper register values or the volatile TCON0 and TCON1 register values (via Increment, Decrement, or
Write commands).
This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High
Voltage commands are required to enable and disable the internal WP EEPROM bit.
1
= EEPROM memory is Write Protected
0
= EEPROM memory can be written
REGISTER 4-1:
STATUS REGISTER (CONTINUED)
Note 1:
Requires a High Voltage command to modify the state of this bit (for Nonvolatile devices only). This bit is
not directly written, but reflects the system state (for this feature).
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