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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCP4242-104E/UN |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 28/88闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DGTL POT DL 100K 2CH 10-MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 绯诲垪锛� | WiperLock™ |
| 鎺ョ墖锛� | 129 |
| 闆婚樆锛堟瓙濮嗭級锛� | 100k |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 150 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闈炴槗澶� |
| 鎺ュ彛锛� | 4 绶� SPI锛堣姱鐗囬伕鎿囷級 |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-MSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 676 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | MCP4242-104-E/UN MCP4242-104-E/UN-ND |
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MCP414X/416X/424X/426X
DS22059B-page 34
2008 Microchip Technology Inc.
REGISTER 4-2:
TCON BITS (1, 2)
R-1
R/W-1
D8
R1HW
R1A
R1W
R1B
R0HW
R0A
R0W
R0B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
bit 8
D8:
Reserved. Forced to 鈥�1鈥�
bit 7
R1HW:
Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the 鈥渟hutdown鈥� configuration of the Hardware pin
1
= Resistor 1 is NOT forced to the hardware pin 鈥渟hutdown鈥� configuration
0
= Resistor 1 is forced to the hardware pin 鈥渟hutdown鈥� configuration
bit 6
R1A:
Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1
= P1A pin is connected to the Resistor 1 Network
0
= P1A pin is disconnected from the Resistor 1 Network
bit 5
R1W:
Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1
= P1W pin is connected to the Resistor 1 Network
0
= P1W pin is disconnected from the Resistor 1 Network
bit 4
R1B:
Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1
= P1B pin is connected to the Resistor 1 Network
0
= P1B pin is disconnected from the Resistor 1 Network
bit 3
R0HW:
Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the 鈥渟hutdown鈥� configuration of the Hardware pin
1
= Resistor 0 is NOT forced to the hardware pin 鈥渟hutdown鈥� configuration
0
= Resistor 0 is forced to the hardware pin 鈥渟hutdown鈥� configuration
bit 2
R0A:
Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1
= P0A pin is connected to the Resistor 0 Network
0
= P0A pin is disconnected from the Resistor 0 Network
bit 1
R0W:
Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1
= P0W pin is connected to the Resistor 0 Network
0
= P0W pin is disconnected from the Resistor 0 Network
bit 0
R0B:
Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1
= P0B pin is connected to the Resistor 0 Network
0
= P0B pin is disconnected from the Resistor 0 Network
Note 1:
The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
2:
These bits do not affect the wiper register values.
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