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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCP4162-104E/MS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 4/88闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC POT DGTL SNGL 100K RHEO 8MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 绯诲垪锛� | WiperLock™ |
| 鎺ョ墖锛� | 257 |
| 闆婚樆锛堟瓙濮嗭級锛� | 100k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 150 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | 4 绶� SPI锛堣姱鐗囬伕鎿囷級 |
| 闆绘簮闆诲锛� | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)鐣�(d膩ng)鍓嶇4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)
MCP414X/416X/424X/426X
DS22059B-page 12
2008 Microchip Technology Inc.
FIGURE 1-2:
SPI Timing Waveform (Mode = 00).
TABLE 1-2:
SPI REQUIREMENTS (MODE = 00)
#
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
鈥�10
MHz VDD = 2.7V to 5.5V
鈥�1
MHz VDD = 1.8V to 2.7V
70
CS Active (VIL or VIHH) to SCK鈫� input
TcsA2scH
60
鈥�
ns
71
SCK input high time
TscH
45
鈥�
ns
VDD = 2.7V to 5.5V
500
鈥�
ns
VDD = 1.8V to 2.7V
72
SCK input low time
TscL
45
鈥�
ns
VDD = 2.7V to 5.5V
500
鈥�
ns
VDD = 1.8V to 2.7V
73
Setup time of SDI input to SCK
鈫� edge
TDIV2scH
10
鈥�
ns
74
Hold time of SDI input from SCK
鈫� edge
TscH2DIL20
鈥�
ns
77
CS Inactive (VIH) to SDO output hi-impedance
TcsH2DOZ鈥�
50
ns
80
SDO data output valid after SCK
鈫� edge
TscL2DOV鈥�
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
82
SDO data output valid after
CS Active (VIL or VIHH)
TssL2doV
鈥�
70
ns
83
CS Inactive (VIH) after SCK鈫� edge
TscH2csI
100
鈥�
ns
VDD = 2.7V to 5.5V
1ms
VDD = 1.8V to 2.7V
84
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
鈥�
ns
Note 1:
This specification by design.
CS
SCK
SDO
SDI
70
71
72
82
SDI
74
75, 76
MSb
BIT6 - - - - - -1
LSb
77
MSb IN
BIT6 - - - -1
LSb IN
80
83
84
73
VIH
VIL
VIHH
VIH
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| M83723/83W2041N | CONN RCPT 41POS WALL MT W/PINS |
| MCP4161-104E/MS | IC POT DGTL SNGL 100K SPI 8MSOP |
| MCP4162-503E/MS | IC POT DGTL SNGL 50K RHEO 8MSOP |
| MCP4162-502E/SN | IC POT DGTL SNGL 5K RHEO 8SOIC |
| MCP4251T-503E/ML | IC DGTL POT 50K 2CH 16QFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MCP4162-104I/MF | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory |
| MCP4162-104I/ML | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory |
| MCP4162-104I/MS | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory |
| MCP4162-104I/P | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory |
| MCP4162-104I/SL | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory |
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