
2003 Microchip Technology Inc.
DS11195C-page 11
MCP41XXX/42XXX
2.1
Parametric Test Circuits
FIGURE 2-25:
Potentiometer Divider Non-
Linearity Error Test Circuit (DNL, INL).
FIGURE 2-26:
Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
FIGURE 2-27:
Wiper Resistance Test
Circuit.
FIGURE 2-28:
Power Supply Sensitivity
Test Circuit (PSS, PSRR).
FIGURE 2-29:
Gain vs. Frequency Test
Circuit.
FIGURE 2-30:
Capacitance Test Circuit.
V+
A
B
W
VMEAS*
V+ = VDD
1LSB = V+/256
DUT
*Assume infinite input impedance
+
-
A
B
W
DUT
IW
*Assume infinite input impedance
VMEAS*
No Connection
+
-
B
DUT
W
+
-
ISW
Rsw = 0.1V
Isw
Code = 00h
0.1V
VSS = 0 to VDD
A
V+
A
B
W
DUT
VA
V+ = VDD ± 10%
PSRR (dB) = 20LOG
VMEAS
)
(
PSS (%/%) =
VDD
VMEAS
VDD
*Assume infinite input impedance
VMEAS*
VDD
+
-
VIN
-
+
+5V
VOUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
VIN
-
+
+5V
VOUT
MCP601
2.5V DC
Offset
A
B
DUT
~