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參數(shù)資料
| 型號(hào)： | MCP3221T |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 560KBITS BRAM 400000 SYSTEM GATES 404 - - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 低功耗12位A / D轉(zhuǎn)換器具有I2C⑩接口 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 520K |
| 代理商： | MCP3221T |
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2003 Microchip Technology Inc.
DS21732B-page 1
M
MCP3221
Features
12-bit resolution
±1 LSB DNL, ±2 LSB INL max.
250 μA max conversion current
5 nA typical standby current, 1 μA max.
I
2
C
compatible serial interface
- 100 kHz I
2
C Standard Mode
- 400 kHz I
2
C Fast Mode
Up to 8 devices on a single 2-Wire bus
22.3 ksps in I
2
C Fast Mode
Single-ended analog input channel
On-chip sample and hold
On-chip conversion clock
Single-supply specified operation: 2.7V to 5.5V
Temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Small SOT-23 package
Applications
Data Logging
Multi-zone Monitoring
Hand-Held Portable Applications
Battery-Powered Test Equipment
Remote or Isolated Data Acquisition
Package Type
Description
The Microchip Technology Inc. MCP3221 is a succes-
sive approximation A/D converter with 12-bit resolu-
tion. Available in the SOT-23 package, this device
provides one single-ended input with very low power
consumption. Based on an advanced CMOS technol-
ogy, the MCP3221 provides a low maximum conver-
sion current and standby current of 250 μA and 1 μA,
respectively. Low current consumption, combined with
the small SOT-23 package, make this device ideal for
battery-powered
and
remote
applications.
data
acquisition
Communication to the MCP3221 is performed using a
2-wire, I
2
C compatible interface. Standard (100 kHz)
and Fast (400 kHz) I
2
C modes are available with the
device. An on-chip conversion clock enables indepen-
dent timing for the I
2
C and conversion clocks. The
device is also addressable, allowing up to eight devices
on a single 2-wire bus.
The MCP3221 runs on a single supply voltage that
operates over a broad range of 2.7V to 5.5V. This
device also provides excellent linearity of ±1 LSB differ-
ential non-linearity and ±2 LSB integral non-linearity,
maximum.
Functional Block Diagram
5-Pin SOT-23A
SCL
AIN
M
1
2
3
5
SDA
V
SS
V
DD
4
Comparator
Sample
and
Hold
12-bit SAR
DAC
I
2
C Interface
AIN
V
SS
V
DD
SCL
SDA
Clock
Control Logic
–
+
Low Power 12-Bit A/D Converter With I
2
C Interface
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