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參數(shù)資料
| 型號： | MCP3221A5T-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2.7V 1CH LP SOT23-5 |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 22.3k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應商設備封裝： | SOT-23-5 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 672 (CN2011-ZH PDF) |
| 配用： | VSUPEV2-ND - BOARD EVAL FOR MCP4022,4023,4024 MXSIGDM-ND - BOARD DEMO PICTAIL MIXED SIGNAL |
| 其它名稱： | MCP3221A5T-E/OTDKR |
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2006 Microchip Technology Inc.
DS21732C-page 17
MCP3221
The input signal will initially be sampled with the first
falling edge of the clock following the transmission of a
logic-high R/W bit. Additionally, with the rising edge of
the SCL, the ADC will transmit an acknowledge bit
(ACK = 0). The master must release the data bus dur-
ing this clock pulse to allow the MCP3221 to pull the
line low (refer to Figure 5-3).
For consecutive samples, sampling begins on the fall-
ing edge of the LSB of the conversion result, which is
two bytes long. Refer to Figure 5-6 a for timing diagram.
5.3.2
READING THE CONVERSION DATA
Once the MCP3221 acknowledges the address byte,
the device will transmit four ‘0’ bits followed by the upper
four data bits of the conversion. The master device will
then acknowledge this byte with an ACK = Low. With the
following 8 clock pulses, the MCP3221 will transmit the
lower eight data bits from the conversion. The master
then sends an ACK = high, indicating to the MCP3221
that no more data is requested. The master can then
send a stop bit to end the transmission.
FIGURE 5-5:
Executing a Conversion.
5.3.3
CONSECUTIVE CONVERSIONS
For consecutive samples, sampling begins on the fall-
ing edge of the LSB of the conversion result. See
Figure 5-6 for timing.
FIGURE 5-6:
Continuous Conversion.
SDA
S
T
A
R
T
S
T
O
P
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
10
0
1
A
R
/
W
Upper Data Byte
00
0
0 D
D
A
C
K
Lower Data Byte
N
A
K
S
P
11 10
2
A
1
A
0
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
12
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
SDA
fSAMP = 22.3 ksps (fCLK = 400 kHz)
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
1
0
1 A2 A1 A0
R
/
W
Upper Data Byte (n)
A
C
K
Lower Data Byte (n)
A
C
K
S
tACQ + tCONV is
initiated here
00
0
0 D
D
11 10 9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
12
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
S
T
A
R
T
0
28
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