To write to a MCP23016 register, the Master I
參數(shù)資料
型號(hào): MCP23016-I/SP
廠商: Microchip Technology
文件頁數(shù): 5/38頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 28SDIP
標(biāo)準(zhǔn)包裝: 15
接口: I²C
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 28-DIP
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 684 (CN2011-ZH PDF)
2007 Microchip Technology Inc.
DS20090C-page 13
MCP23016
1.9.2
WRITING THE REGISTERS
To write to a MCP23016 register, the Master I2C device
needs to follow the requirements, as illustrated in
Figure 1-3. First, the device is selected by sending the
slave address and setting the R/W bit to logic ‘0’. The
command byte
is
sent
after
the
address
and
determines which register will be written. Table 1-3
shows the relationship of the command byte and
register.
The MCP23016 has twelve 8-bit registers. They are
configured to operate as six 16-bit register pairs,
supporting the device’s 16-bit port. These pairs are
formed based on their functions (e.g., GP0 and GP1
are grouped together). The I2C commands apply to one
register pair to provide faster access. The first data byte
following a command byte is written into the register
pointed to by the command byte, while the second data
is written into another register in the same pair. For
example, if the first byte is sent to OLAT1 (command
byte 03h), the next data byte will be written into the sec-
ond register of that pair, OLAT0. If the first byte is writ-
ten to OLAT0 (command byte 02h), the second byte
will be written to OLAT1.
There is no limitation on the number of data bytes in
one write transmission. Figure 1-4 shows the case of
multiple byte writes in one write operation. In this case,
the multiple writes are made to the same data pair.
FIGURE 1-3:
WRITE TO CONFIGURATION
REGISTERS (CASE 1)
Note:
The bus must remain free until after the
ninth clock pulse for a minimum of 12 s
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
A2
A1
A0
D0
S
0
R/
W
=0
ACK
D6
D5
D4
D3
D2
D1
D7
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D0
D6
D5
D4
D3
D2
D1
D7
ACK
D0
D6
D5
D4
D3
D2
D1
D7
ACK
P
Ad
d
re
s
C
o
mm
and
B
y
te
Da
ta
1
D
a
ta
2
ACK
SCL
h
e
ld
lo
w
u
n
til
data
i
s
pro
c
esse
d
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