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參數(shù)資料
| 型號： | MCM72PB8ML3.5R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 72 Bit Burst RAM Multichip Module |
| 中文描述： | 256K X 72 CACHE SRAM MODULE, 3.5 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MCM72PB8ML3.5R |
MCM72FB8ML MCM72PB8ML
9
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time (See Figure 3)
1.25 V
0 to 2.5 V
. . . . . . . . . . . . . .
1.0 V/ns (20 to 80%)
. . . . . . . . .
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1 and 2)
Parameter
Symbol
b l
Pipeline
MCM72PB8ML3.5
166 MHz
Pipeline
MCM72PB8ML4
133 MHz
Flow–Through
MCM72FB8ML7.5
117 MHz
Flow–Through
MCM72FB8ML8
100 MHz
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
6
—
7.5
—
8.5
—
10
—
ns
Clock High Pulse Width
2.4
—
3
—
3.4
—
4
—
ns
3
Clock Low Pulse Width
2.4
—
3
—
3.4
—
4
—
ns
3
Clock Access Time
—
3.5
—
4
—
7.5
—
8
ns
Output Enable to Output
Valid
—
3.5
—
3.8
—
3.5
—
3.5
ns
Clock High to Output Active
tKHQX1
tKHQX2
0
—
0
—
0
—
0
—
ns
4, 5
Clock High to Output
Change
1.5
—
1.5
—
2
—
2
—
ns
4
Output Enable to Output
Active
tGLQX
0
—
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
tKHQZ
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
—
3.5
—
3.8
—
3.5
—
3.5
ns
4, 5
Clock High to Q High–Z
1.5
6
1.5
7.5
2
3.5
2
3.5
ns
4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
1.5
—
1.5
—
2
—
2
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at
±
200 mV from steady state.
OUTPUT
Z0 = 50
RL = 50
1.25 V
Figure 2. AC Test Load
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