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參數(shù)資料
| 型號： | MCM72FB8ML7.5 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 72 Bit Burst RAM Multichip Module |
| 中文描述： | 256K X 72 CACHE SRAM MODULE, 7.5 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MCM72FB8ML7.5 |
MCM72FB8ML MCM72PB8ML
16
MOTOROLA FAST SRAM
K
ADSC
ADDRESS
WRITE
A1
A2
ADSC
(INITIATES
BURST WRITE)
CLOCK STOP
(CONTINUE
BURST WRITE)
WAKE UP ADSC
(INITIATES BURST WRITE)
D(A1)
DATA IN
D(A1 + 1)
D(A2)
DQx
HIGH–Z
ADV
VIH OR VIL FIXED (SEE NOTE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
STOP CLOCK WITH WRITE TIMING
相關PDF資料 |
PDF描述 |
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| MCM72FB8ML7.5R | CAP CER 680PF 100V C0G 0603 |
| MCM72FB8ML | 600000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| MCM72FB8ML8 | 600,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| MCR102 | Silicon Controlled Rectifiers |
| MCR103 | Silicon Controlled Rectifiers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCM72FB8ML8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72FB8ML8R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72JG32 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium |
| MCM72JG32SG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium |
| MCM72JG64SG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium |
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