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參數(shù)資料
| 型號： | MCM72BF32SG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Module for Pentium |
| 中文描述： | 64K X 36 CACHE SRAM MODULE, 9 ns, DMA160 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 167K |
| 代理商： | MCM72BF32SG66 |
MCM72F8
MCM72F9
6
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
Vin, Vout
VIT
Iout
PD
– 0.5 to + 4.6
V
Voltage Relative to VSS (See Note 2)
Input Voltage Three State I/O (See Note 2)
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
20
V
V
Output Current (per I/O)
mA
Power Dissipation
MCM72F8
MCM72F9
4.6
9.2
W
Ambient Temperature
TA
TJ
0 to 70
°
C
Die Temperature
110
°
C
Temperature Under Bias
Tbias
Tstg
– 10 to + 85
°
C
Storage Temperature
– 55 to + 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing cannot be controlled and is
not allowed.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VDD
VIH
VIL
3.135
3.3
3.6
V
Input High Voltage
1.7
—
VDD + 0.3
0.7
V
Input Low Voltage
– 0.3*
—
V
* VIL
≥
– 2.0 V for t
≤
tKHKH/2.
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 1. Undershoot Voltage
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (0 V
≤
Vin
≤
VDD)
Output Leakage Current (0 V
≤
Vin
≤
VDD)
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
Ilkg(I)
Ilkg(O)
VOL
VOH
—
±
1.0
μ
A
—
±
1.0
μ
A
—
0.4
V
2.4
—
V
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated volt-
ages to this high–impedance circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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