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參數(shù)資料
| 型號： | MCM69L818AZP8.5R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT07; Number of Contacts:8; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle |
| 中文描述： | 256K X 18 CACHE SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 225K |
| 代理商： | MCM69L818AZP8.5R |
MCM69L736A
MCM69L818A
12
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of CK. These signals must meet the setup and hold
times shown in the AC Characteristics table. On the falling
edge of the current cycle, the output latch becomes trans-
parent and data is available. The output data is latched on
the rising edge of the next clock. The output data is available
at the output at tKLQV or tKHQV, whichever is later.
tKHQV is the internal latency of the device. During this same
cycle, a new read address can be applied to the address
pins.
A write cycle can occur on the next cycle as long as
tKLQX and tDVKH are met. Read cycles may follow write
cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of CK has its effect on the out-
put drivers immediately. SW low deselects the output drivers
immediately (on the same cycle). Output selecting via a low
on SS and high on SW at a rising CK has its effect on the
output drivers at tKLQX. Output drive is also controlled direct-
ly by output enable (G). G is an asynchronous input. No clock
edges are required to enable or disable the output with G.
Output data will be valid at tGLQV, tKHQV, or tKLQV, which is
even later. Outputs will begin driving at tKLQX1. Outputs will
hold previous data until tKLQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable in-
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250
resistor will give an output
impedance of 50
.
Impedance updates occur continuously and the frequency
of the update is based on the subdivided K clock. Note that if
the K clock stops so does the impedance update.
The actual change in the impedance occurs in small incre-
ments and is monotonic. There are no significant distur-
bances that occur on the output because of this smooth
update method.
The impedance update is not related to any particular type
of cycle because the impedance is updated continuously and
is based on the K clock. Updates occur regardless of wheth-
er the the device is performing a read, write or a deselect
cycle and does not depend on the state of G.
At power up, the output impedance defaults to approxi-
mately 50 ohms. It will take 4,000 to 16,000 cycles for the im-
pedance to be completely updated if the programmed
impedance is much higher or lower than 50
.
The output buffers can also be programmed in a minimum
impedance configuration by connecting ZQ to VDD.
POWER UP AND INITIALIZATION
Once supplies have reached specification levels, a
minimum dwell of 1.0
μ
s with CK inputs cycling is required
before beginning normal operations. At power up the output
impedance will be set at approximately 50
, however, in
order to match the programmed impedance the part requires
deselect cycles to occur.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM69L736AZP7.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT07; No. of Contacts:8; Connector Shell Size:16; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| MCM69L818AZP7.5 | 4M Late Write HSTL |
| MCM69L736A | 4M Late Write HSTL |
| MCM69L738AZP8.5 | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:4; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:12-4 |
| MCM69L738AZP9.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69L818AZP9.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L818AZP9.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L819AZP8.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69L819AZP8.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69L819AZP9 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
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