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參數(shù)資料
| 型號： | MCM69L818AZP10.5 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | ER 23C 16 12 8 4 SKT PLUG |
| 中文描述： | 256K X 18 CACHE SRAM, 10.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 225K |
| 代理商： | MCM69L818AZP10.5 |
MCM69L736A
MCM69L818A
13
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE 1149.1–1990 (commonly referred to as JTAG), but
does not implement all of the functions required for 1149.1
compliance. Certain functions have been modified or elimi-
nated because their implementation places extra delays in
the RAMs critical speed path. Nevertheless, the RAM sup-
ports the standard TAP controller architecture. The TAP con-
troller is the state machine that controls the TAP operation
and can be expected to function in a manner that does not
conflict with the operation of devices with IEEE 1149.1
compliant TAPs. The TAP operates using conventional
JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS logic
level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic one, and may be left unconnected. But they may also
be tied to VDD through a 1 k resistor. TDO should be left
unconnected.
TAP DC OPERATING CHARACTERISTICS
(0 C
≤
TA
≤
70 C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Notes
Logic Input Logic High
VIH1
VIL1
Ilkg
VOL1
VOH1
VOL2
VOH2
2.0
VDD + 0.3
0.8
V
Logic Input Logic Low
– 0.3
V
Logic Input Leakage Current
—
±
5
μ
A
1
CMOS Output Logic Low
—
0.2
V
2
CMOS Output Logic High
VDD – 0.2
—
—
V
3
TTL Output Logic Low
0.4
V
4
TTL Output Logic High
2.4
—
V
5
NOTES:
1. 0 V
±
Vin
±
VDDQ for all logic input pins.
2. IOL1
≤
100
μ
A @ VOL = 0.2 V. Sampled, not 100% tested.
3.
IOH1
≤
100
μ
A @ VDDQ – 0.2 V. Sampled, not 100% tested.
4. IOL2
≤
8 mA @ VOL = 0.4 V.
5.
IOH2
≤
8 mA @ VOH = 2.4 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM69L736AZP10.5R | 4M Late Write HSTL |
| MCM69L818AZP10.5R | 4M Late Write HSTL |
| MCM69L736AZP9.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MCM69L818AZP9.5 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MCM69L736AZP9.5R | Circular Connector; No. of Contacts:2; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:10-2 |
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參數(shù)描述 |
|---|---|
| MCM69L818AZP7.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L818AZP7.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L818AZP8.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L818AZP8.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69L818AZP9.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
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