參數(shù)資料
型號: MCM69L736AZP10.5
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 4M Late Write HSTL
中文描述: 128K X 36 CACHE SRAM, 10.5 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁數(shù): 9/20頁
文件大?。?/td> 225K
代理商: MCM69L736AZP10.5
MCM69L736A
MCM69L818A
9
MOTOROLA FAST SRAM
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 4)
VIH (ac)
Vref + 200 mV
AC Input Logic Low (See Figures 2 and 4)
VIL (ac)
Vref – 200 mV
1
Input Reference Peak to Peak ac Voltage
Vref (ac)
5% Vref (dc)
2
Clock Input Differential Voltage
Vdif (ac)
400 mV
VDDQ + 600 mV
3
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
VOH
VSS
50%
100%
20% tKHKH
Figure 2. Undershoot Voltage
CROSSING POINT
VDDQ
VSS
VTR
VDIF
VCP
VCM*
Figure 3. Differential Inputs/Common Mode Input Voltage
*VCM, the Common Mode Input Voltage, equals VTR – ((VTR – VCP)/2).
VIH(ac)
Vref
VIL(ac)
Figure 4. Differential Inputs/Common Mode Input Voltage
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