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    • 參數(shù)資料
      型號: MCM69L736A
      廠商: Motorola, Inc.
      英文描述: 4M Late Write HSTL
      中文描述: 4分后寫入HSTL
      文件頁數(shù): 7/20頁
      文件大?。?/td> 225K
      代理商: MCM69L736A
      MCM69L736A
      MCM69L818A
      7
      MOTOROLA FAST SRAM
      DC OUTPUT BUFFER CHARACTERISTICS – PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
      (0 C
      TA
      70 C, Unless Otherwise Noted, See Notes 5 and 6)
      Parameter
      Symbol
      Min
      Max
      Unit
      Notes
      Output Logic Low
      VOL
      VDDQ/2 – 0.025
      VDDQ/2 +0.025
      V
      1
      Output Logic High
      VOH
      VDDQ/2 – 0.025
      VDDQ/2 + 0.025
      V
      2
      Light Load Output Logic Low
      VOL1
      VSS
      0.2
      V
      3
      Light Load Output Logic High
      VOH1
      VDDQ – 0.2
      VDDQ
      V
      4
      NOTES:
      1. IOL = (VDDQ/2)/(RQ/5) for values of RQ = 175
      RQ
      350
      .
      2. | IOH | = (VDDQ/2)/(RQ/5) for values of RQ = 175
      RQ
      350
      .
      3. IOL
      100
      μ
      A.
      4. | IOH |
      100
      μ
      A.
      5. The impedance controlled mode is expected to be used in point–to–point applications, driving high impedance inputs.
      6. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
      DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
      (0 C
      TA
      70 C, ZQ = VDD)
      (See Notes 1 and 2)
      Parameter
      Symbol
      Min
      Max
      Unit
      Notes
      Output Logic Low
      VOL2
      VSS
      0.4
      V
      3
      Output Logic High
      VOH2
      VDDQ – 0.4
      VDDQ
      V
      4
      Light Load Output Logic Low
      VOL3
      VSS
      0.2
      V
      5
      Light Load Output Logic High
      VOH3
      VDDQ – 0.2
      VDDQ
      V
      6
      NOTES:
      1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
      Standard JESD8–6 Class I.
      2. The ZQ pin is connected to VDD to enable the minimum impedance mode.
      3. IOL
      8 mA.
      4.
      IOH
      8 mA.
      5. IOL
      100
      μ
      A.
      6.
      IOH
      100
      μ
      A.
      CAPACITANCE
      (f = 1.0 MHz, dV = 3.0 V, 0 C
      TA
      70 C, Periodically Sampled Rather Than 100% Tested)
      Characteristic
      Symbol
      Typ
      Max
      Unit
      Input Capacitance
      Cin
      CI/O
      CCK
      4
      5
      pF
      Input/Output Capacitance
      7
      8
      pF
      CK, CK Capacitance
      4
      5
      pF
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