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參數(shù)資料
| 型號： | MCM67Q709A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128Kx9 Bit Synchronous Fast Static RAM(128Kx9 Bit同步快速靜態(tài)存儲器) |
| 中文描述： | 128Kx9位同步快速靜態(tài)存儲器（128Kx9位同步快速靜態(tài)存儲器） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 145K |
| 代理商： | MCM67Q709A |
MCM67Q709A
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1a Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
Parameter
Symbol
b l
MCM67Q709A–10
U i
Unit
Notes
Min
Max
Cycle Time
tKHKH
tKHQV
tKLKH
tKHKL
tKHQX
tKHQZ
tAVKH
tWVKH
tEVKH
tGVKH
tDVKH
10
—
ns
1
Clock Access Time
—
5
ns
2
Clock Low Pulse Width
4
—
ns
Clock High Pulse Width
4
—
ns
Clock High to Data Output Invalid
2
—
ns
Clock High to Data Output High–Z
—
5
ns
3
Setup Times:
A
W
E
G
D0 – D8
2
—
ns
4
Hold Times:
A
W
E
G
D0 – D8
tKHAX
tKHWX
tKHEX
tKHGX
tKHDX
1
—
ns
4
NOTES:
1. All read and write cycles are referenced from K.
2. Valid data from clock high will be the data stored at the address or the last valid read cycle.
3. Measured at
±
200 mV from steady state. Tested per High–Z test load (See Figure 1b).
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for
ALL
rising
edges of clock (K) while the device is selected.
(b)
5 pF
+ 5 V
OUTPUT
255
480
(a)
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. Test Loads
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