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參數(shù)資料
| 型號： | MCM63Z737 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M Bit Synchronous Fast Static RAM(4M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 4分位同步快速靜態(tài)存儲器（4分位同步遲寫快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MCM63Z737 |
MCM63Z737 MCM63Z819
11
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0
°
to 70
°
C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
VDDQ*
TA
VIL
VIH
VIH2
3.135
3.3
3.465
V
I/O Supply Voltage
3.135
3.3
VDD
70
V
Ambient Temperature
0
—
°
C
Input Low Voltage
–0.3
—
0.8
V
Input High Voltage
2
—
VDD + 0.3
VDDQ + 0.3
V
Input High Voltage I/O Pins
2
—
V
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
≤
Vin
≤
VDD)
Output Leakage Current (0 V
≤
Vin
≤
VDDQ)
AC Supply Current (Device Selected
All Outputs Open, Freq = Max) Includes
Supply Current for Both VDD and VDDQ
Ilkg(I)
Ilkg(O)
IDDA
—
—
±
1
μ
A
1
—
—
±
1
μ
A
MCM63Z737/819–10,
MCM63Z737/819–11
MCM63Z737/819–15
—
—
335
315
305
mA
2, 3, 4
Hold Supply Current (Device Selected, Freq = Max,
VDD = Max, VDDQ = Max, CKE
≥
VDD – 0.2 V,
All Inputs Static at CMOS Levels)
IDD1
—
—
80
mA
6
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels)
ISB2
—
—
40
mA
5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
—
—
145
mA
5, 7
Clock Running (Device Deselected,
Freq = Max, VDD = Max,
All Inputs Toggling at CMOS Levels)
MCM63Z737/819–10
MCM63Z737/819–11
MCM63Z737/819–15
ISB4
—
—
245
235
225
mA
5, 7
Output Low Voltage (IOL = 8 mA)
Output High Voltage (IOH = –8 mA)
NOTES:
1. LBO has an internal pullup and will exhibit leakage currents of
±
5
μ
A.
2. Reference AC Operating Conditions and Characteristics for Input and Timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the Truth Table.
6. CMOS levels for I/O’s are VIT
≤
VSS + 0.2 V or
≥
VDDQ – 0.2 V. CMOS levels for other inputs are Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V.
7. TTL levels for I/O’s are VIT
≤
VIL or
≥
VIH2. TTL levels for other inputs are Vin
≤
VIL or
≥
VIH.
VOL
VOH
—
—
0.4
V
2.4
—
—
V
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