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參數(shù)資料
| 型號(hào)： | MCM63P733ATQ133R |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | ER 5C 5#16S PIN RECP |
| 中文描述： | 128K X 32 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | MCM63P733ATQ133R |
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MCM63P733A
6
MOTOROLA FAST SRAM
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
SW
SBa
SBb
SBc
SBd
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte a
H
L
L
H
H
H
Write Byte b
H
L
H
L
H
H
Write Byte c
H
L
H
H
L
H
Write Byte d
H
L
H
H
H
L
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Notes
Power Supply Voltage
VDD
VDDQ
Vin, Vout
– 0.5 to + 4.6
V
I/O Supply Voltage
VSS – 0.5 to VDD
– 0.5 to VDD + 0.5
V
2
Input Voltage Relative to VSS for
Any Pin Except VDD
V
2
Input Voltage (Three–State I/O)
VIT
Iout
PD
Tbias
Tstg
– 0.5 to VDDQ + 0.5
±
20
V
2
Output Current (per I/O)
mA
Package Power Dissipation
1.2
W
3
Temperature Under Bias
– 10 to + 85
°
C
Storage Temperature
– 55 to + 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
R
θ
JA
40
25
°
C/W
1, 2
Junction to Board (Bottom)
R
θ
JB
R
θ
JC
17
°
C/W
3
Junction to Case (Top)
9
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
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