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參數(shù)資料
| 型號(hào)： | MCM63L836A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 8MBit快速同步后寫入靜態(tài)存儲(chǔ)器（800萬位同步遲寫快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MCM63L836A |
MCM63L836A
MCM63L918A
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(3.0 V
≤
VDD
≤
3.6 V, 0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Max
–3.8
Max
–4.0
Max
–4.2
Max
–4.5
Max
–5.0
Max
Unit
Notes
Core Power Supply Voltage
VDD
VDDQ
IDD1
3.0
—
—
—
—
—
3.6
V
Output Driver Supply Voltage
1.8
—
—
—
—
—
2.0
V
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max,
VDD = Max, VDDQ = Max). Includes
Supply Currents for VDD.
Quiescent Active Power Supply
Current (Device Selected, All Outputs
Open, Freq = 0, VDD = Max,
VDDQ = Max). Includes Supply
Currents for VDD.
—
600
580
560
540
520
600
mA
5
IDD2
—
175
175
175
175
175
175
mA
6
Active Standby Power Supply
Current (Device Deselected,
Freq = Max, VDD = Max,
VDDQ = Max).
CMOS Standby Supply Current
(Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max,
All Inputs Static at CMOS Levels).
ISB1
—
200
195
190
185
180
200
mA
7
ISB2
—
175
175
175
175
175
175
mA
6, 7
Sleep Mode Current (ZZ = VIH,
VDD = Max, VDDQ = Max)
IZZ
—
45
45
45
45
45
45
mA
6, 7
Input Reference DC Voltage
Vref (dc)
0.7
—
—
—
—
—
1.0
V
8
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. All inputs are zero.
6. CMOS levels for I/Os are VIC
≤
VSS + 0.2 V or
≥
VDDQ – 0.2 V.
7. Device deselected as defined by the Clock Truth Table.
8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-
nent superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg(I)
Vin (dc)
VDIF (dc)
VCM (dc)
Vref + 0.1
–0.3
VDDQ + 0.3
Vref – 0.1
±
5
V
DC Input Logic Low
V
1
Input Leakage Current
—
μ
A
2, 3
Clock Input Signal Voltage
–0.3
2.5
V
Clock Input Differential Voltage (See Figure 3)
0.2
2.5
V
4
Clock Input Common Mode Voltage Range (See Figure 3)
0.60
1.1
V
5
NOTES:
1. Inputs may undershoot to –1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See Figure 2.
2. 0 V
≤
Vin
≤
VDDQ for all pins.
3. Measured at Vref = 0.75 V.
4. Minimum instantaneous differential input voltage required for differential input clock operation.
5. Maximum rejectable common mode input voltage variation.
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