參數資料
型號: MCIMX357DJQ5CR2
廠商: Freescale Semiconductor
文件頁數: 118/147頁
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標準包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數: 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
72
4.9.13.2
Interface to Sharp HR-TFT Panels
Figure 51 depicts the Sharp HR-TFT panel interface timing, and Table 57 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Table 56. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min.
Typ.1
1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Max.
Units
IP16 Display interface clock low time
Tckl
Tdicd – Tdicu – 1.5
Tdicd2 –Tdicu3
2 Display interface clock down time
3 Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
Tdicd – Tdicu + 1.5
ns
IP17 Display interface clock high time
Tckh
Tdicp – Tdicd +
Tdicu–1.5
Tdicp–Tdicd +
Tdicu
Tdicp–Tdicd +
Tdicu + 1.5
ns
IP18 Data setup time
Tdsu
Tdicd – 3.5
Tdicu
ns
IP19 Data holdup time
Tdhd
Tdicp – Tdicd – 3.5
Tdicp – Tdicu
ns
IP20 Control signals setup time to
display interface clock
Tcsu
Tdicd – 3.5
Tdicu
ns
Tdicd
1
2
---T
HSP_CLK
ceil
2 DISP3_IF_CLK_DOWN_WR
HSP_CLK_PERIOD
---------------------------------------------------------------------------------
=
Tdicu
1
2
---T
HSP_CLK
ceil
2 DISP3_IF_CLK_UP_WR
HSP_CLK_PERIOD
----------------------------------------------------------------------
=
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