參數(shù)資料
型號： MCIMX31LVMN5C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 532 MHz, MICROPROCESSOR, PBGA473
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-473
文件頁數(shù)： 37/122頁
文件大?。?/td> 1418K
代理商： MCIMX31LVMN5C
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
21
Figure 3. Option 1 Power-Up Sequence (Silicon Revision 2.0)
Figure 4. Option 2 Power-Up Sequence (Silicon Revision 2.0)
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
Hold POR Asserted
1, 3, 5
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
3
The parallel paths in the flow indicate that supply group
NVCC2, NVCC21, and NVCC22, and supply group
FVCC, MVCC, SVCC, and UVCC ramp-ups are
independent. Note that this power-up sequence is
backward compatible to Silicon Revs. 1.15 and 1.2,
because NVCC2x ramp-up proceeding PLL supplies is
allowed.
4
Unlike the power-up sequence for Silicon Revision 1.2,
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
5
Raising IOQVDD before NVCC21 produces a slight
increase in current drain on IOQVDD of approximately
3–5 mA. The current increase will not damage the IC.
Refer to Errata ID TLSbo91750 for details.
FVCC, MVCC, SVCC, UVCC
4
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22
Hold POR Asserted
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
3
Raising NVCC2, NVCC21, and NVCC22 at the same
time as IOQVDD does not produce the slight increase in
current drain on IOQVDD (as described in Figure 3,
Note 5).
4
Unlike the power-up sequence for Silicon Revision 1.2,
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
FVCC, MVCC, SVCC, UVCC
4
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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