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參數(shù)資料
| 型號： | MCIMX27LMOP4A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/152頁 |
| 文件大小： | 0K |
| 描述： | IC MPU I.MX27 IN 19X19 473MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | i.MX27 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 400MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，LCD，POR，PWM，WDT |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 45K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.38 V ~ 1.52 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 473-LFBGA |
| 包裝： | 托盤 |
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i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
13
Functional Description and Application Information
Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the
camera (for Bayer data only)
2.3.9
Configurable Serial Peripheral Interface (CSPI)
The Configurable Serial Peripheral Interface (CSPI) is used for fast data communication with fewer
software interrupts. There are three CSPI modules in the i.MX27/MX27L processors, which provide a
full-duplex synchronous serial interface, capable of interfacing to the SPI master and slave devices. CSPI1
and CSPI2 are master/slave configurable and include three chip selects to support multiple peripherals.
CSPI3 is only a master and has one chip-select signal. The transfer continuation function of the CSPI
enables unlimited length data transfers using 32-bit wide by 8-entry FIFO for both TX and RX data DMA
support.
The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with
fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer
data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer
data between these two devices. When the CSPI module is configured as a slave, the user can configure
the CSPI Control register to match the external SPI master’s timing.
2.3.10
Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D
memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.
Features include the following:
Support of 16 channels linear memory, 2D memory, and FIFO for both source and destination
Support of 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
Configurability of DMA burst length of up to a maximum of 16 words, 32 half-words, or 64 bytes
for each channel
Bus utilization control for a channel that is not triggered by DMA request
Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error
DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a
programmed timing period
Dedicated external DMA request and grant signal
Support of increment, decrement, and no increment for source and destination addressing
Support of DMA chaining
2.3.11
enhanced MultiMedia Accelerator Light (eMMA_lt)
The enhanced MultiMedia Accelerator Light (eMMA_lt) consists of the video pre-processor (PrP) and
post-processor (PP). In contrast with i.MX21 processor’s components, this eMMA does not include the
video codec. A more powerful video codec is included as a separate module.
NOTE
The i.MX27L does not have a eMMA_lt module.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX27LMOP4AR2 | 功能描述:開發(fā)板和工具包 - ARM LW CostBONO IN 19X19 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX27LOVP4A | 制造商:Freescale Semiconductor 功能描述: |
| MCIMX27LPDK | 功能描述:開發(fā)板和工具包 - ARM MCIMX27 PDK For LINUX RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX27LV0P4A | 制造商:Freescale Semiconductor 功能描述: |
| MCIMX27LVJP4A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
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