參數(shù)資料
型號(hào)： MCIMX258CVM4
廠商： Freescale Semiconductor
文件頁數(shù)： 151/153頁
文件大?。?/td> 0K
描述： IC MPU I.MX25 IND 400MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： i.MX25
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 128
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
RAM 容量： 144K x 8
電壓 - 電源 (Vcc/Vdd)： 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 400-LFBGA
包裝： 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
97
3.7.14.1
SIM Reset Sequences
SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences
in these two cases.
3.7.14.1.1
SIM Cards with Internal Reset
Figure 69 shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the
following steps:
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between
400–40000 clock cycles after T0.
Figure 69. Internal Reset Card Reset Sequence
Table 75 defines the general timing requirements for the SIM interface.
3.7.14.1.2
SIM Cards with Active Low Reset
Figure 70 shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the
following steps:
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be
received on RX during those 40,000 clock cycles)
SIMx_RSTy is asserted (at time T1)
SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.
Table 75. Timing Specifications, Internal Reset Card Reset Sequence
Ref No.
Min.
Max.
Units
1
—
200
clk cycles
2
400
40,000
clk cycles
SIMn_SVENm
SIMx_CLKy
SIMx_DATAy_RX_TX
2
T0
RESPONSE
1
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