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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCIMX257CVM4
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 140/153闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MPU I.MX25 IND 400MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� i.MX25
鏍稿績铏曠悊鍣細 ARM9
鑺珨灏哄锛� 32-浣�
閫熷害锛� 400MHz
閫i€氭€э細 1 绶�(xi脿n)锛孋AN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孖²S锛孡CD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 128
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灏佽/澶栨锛� 400-LFBGA
鍖呰锛� 鎵樼洡(p谩n)
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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
87
1 FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
3.7.9.2
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58 shows MII asynchronous input timings. Table 65 describes the timing parameters (M10鈥擬15)
shown in the figure.
Figure 58. MII Serial Management Channel Timing Diagram
Table 64. MII Asynchronous Inputs Signal Timing
ID
Characteristic
Min.
Max.
Unit
M91
FEC_CRS to FEC_COL minimum pulse width
1.5
鈥�
FEC_TX_CLK period
Table 65. MII Serial Management Channel Timing
ID
Characteristic
Min.
Max.
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
0鈥�
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
鈥�5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
鈥�
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
鈥�
ns
M14
FEC_MDC pulse width high
40%
60%
FEC_MDC period
M15
FEC_MDC pulse width low
40%
60%
FEC_MDC period
FEC_MDC (output)
FEC_MDIO (output)
M14
M15
M10
M11
M12
M13
FEC_MDIO (input)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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