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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCIMX253DVM4
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 16/153闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MPU I.MX25 COMM 400MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� i.MX25
鏍稿績铏曠悊鍣細 ARM9
鑺珨灏哄锛� 32-浣�
閫熷害锛� 400MHz
閫i€氭€э細 1 绶�锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孖²S锛孡CD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 128
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 澶栭儴绋嬪簭瀛樺劜(ch菙)鍣�
RAM 瀹归噺锛� 144K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.15 V ~ 1.52 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 3x12b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -20°C ~ 70°C
灏佽/澶栨锛� 400-LFBGA
鍖呰锛� 鎵樼洡
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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
112
Freescale Semiconductor
assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
Figure 82. Start-up Sequence
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising
edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,
xnsw) are totally asynchronous.
The following conditions are necessary to guarantee the correct operation of the ADC:
The input multiplexer selection (selin11鈥elin0) is stable during both the last clock cycle (14th)
and the first clock cycle (1st). The best way to guarantee this is to make the input multiplexer
selection during clock cycles 2 to 13.
The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the
reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it
only after an eoc pulse has been acquired, during the last clock cycle (14).
鐩搁棞(gu膩n)PDF璩囨枡
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