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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCIMX251AVM4 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 132/140闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU I.MX25 AUTO 400MAPBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | i.MX25 |
| 鏍稿績铏曠悊鍣細 | ARM9 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 400MHz |
| 閫ｉ€氭€э細 | 1 绶氾紝CAN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孖²S锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 128 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 澶栭儴绋嬪簭瀛樺劜(ch菙)鍣� |
| RAM 瀹归噺锛� | 144K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.15 V ~ 1.52 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 3x12b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 400-LFBGA |
| 鍖呰锛� | 鎵樼洡 |
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i.MX25 Applications Processor for Automotive Products, Rev. 10
Freescale Semiconductor
91
3.7.11
Inter IC Communication (I2C) Timing
The I2C communication protocol consists of the following seven elements:
Start
Data source/recipient
Data direction
Slave acknowledge
Data
Data acknowledge
Stop
parameters (IC1鈥揑C6) shown in the figure.
Figure 64. I2C Module Timing Diagram
Table 69. I2C Module Timing Parameters: 3.0 V +/鈥�0.30 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
IC1
I2CLK cycle time
10
-
2.5
渭s
IC2
Hold time (repeated) START condition
4.0
-
0.6
-
渭s
IC3
Set-up time for STOP condition
4.0
-
0.6
-
渭s
IC4
Data hold time
01
3.452
01
0.92
渭s
IC5
HIGH Period of I2CLK Clock
4.0
-
0.6
-
渭s
IC6
LOW Period of the I2CLK Clock
4.7
-
1.3
-
渭s
IC7
Set-up time for a repeated START condition
4.7
-
0.6
-
渭s
IC8
Data set-up time
250
-
1003
-ns
IC9
Bus free time between a STOP and START condition
4.7
-
1.3
-
渭s
IC10
Rise time of both I2DAT and I2CLK signals
-
1000
20+0.1Cb
4
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
-
300
20+0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
-
400
-
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
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| MCIMX253CJM4 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� IMX25 INDUSTRIAL RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX253CJM4A | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� IMX25 1.2 INDUST RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
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