參數(shù)資料
型號(hào): MCHC705KJ1CPE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 72/108頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT 64 BYTES RAM 16PDIP
標(biāo)準(zhǔn)包裝: 25
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 10
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類(lèi)型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 管件
Parallel I/O Ports (PORTS)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
66
Freescale Semiconductor
7.2.4 Port LED Drive Capability
All outputs can drive light-emitting diodes (LEDs). These pins can sink approximately 10 mA of current to
VSS.
7.2.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1, PA0–PA3 pins function as external
7.3 Port B
Port B is a 2-bit bidirectional port.
7.3.1 Port B Data Register
The port B data register contains a latch for each port B pin.
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
NOTE
PB4–PB5 and PB0–PB1 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring
them as inputs will ensure that the pulldown devices are enabled, thus
properly terminating them.
Address:
$0001
Bit 7
654321
Bit 0
Read:
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will ensure
that the pulldown devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
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