參數(shù)資料
型號(hào): MCF5475
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: MCF547x Integrated Microprocessor Electrical Characteristics
中文描述: MCF547x集成的微處理器,電氣特性
文件頁(yè)數(shù): 11/28頁(yè)
文件大?。?/td> 706K
代理商: MCF5475
SDRAM Bus
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
11
Figure 7. FlexBus Write Timing
9
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.
9.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read
cycles. The MCF547
x
SDRAM controller is a DDR controller that has an SDR mode. Because it is
designed to support DDR, a DQS pulse must still be supplied to the MCF547
x
for each data beat of an
SDR read. The MCF547
x
accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SDR_DQS signal and its usage.
CLKIN
AD[X:0]
AD[31:Y]
R/W
ALE
TSIZ[1:0]
FBCSn, BE/BWEn
TA
FB1
A[X:0]
A[31:Y]
DATA
FB2
FB3
TSIZ[1:0]
FB3
FB6
FB7
OE
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