參數(shù)資料
型號(hào): MCF5470ZP200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, MS-034AAL-1, PBGA-388
文件頁(yè)數(shù): 34/34頁(yè)
文件大?。?/td> 600K
代理商: MCF5470ZP200
Hardware Design Considerations
MCF547x ColdFire Microprocessor, Rev. 4
Freescale Semiconductor
9
4.4
USB Power Filtering
To minimize noise, an external filter is required for each of the USB power pins. The filter shown in Figure 6 should be
connected between the board EVDD or IVDD and each of the USB VDD pins.
The resistor and capacitors should be placed as close to the dedicated USB VDD pin as possible.
A separate filter circuit should be included for each USB VDD pin, a total of five circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
The filter for USB_PHYVDD to VSS should be connected to the power and ground planes, respectively, not fingers
of the planes.
In addition to keeping the filter components for the USB_PLLVDD as close as practical to the body of the processor
as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital
switching noise onto the portion of that supply between the filter and the processor.
The capacitors for C2 in the table below should be rated X5R or better due to temperature performance.
Figure 6. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
Table 5 lists the resistor values and supply voltages to be used in the circuit for each of the USB VDD pins.
Table 5. USB Filter Circuit Values
USB VDD Pin
Nominal Voltage
R1 (
Ω)C1 (μF)
C2 (
μF)
USBVDD
(Bias generator supply)
3.3V
10
0.1
USB_PHYVDD
(Main transceiver supply)
3.3V
0
10
0.1
USB_PLLVDD
(PLL supply)
1.5V
10
1
0.1
USB_OSCVDD
(Oscillator supply)
3.3V
0
10
0.1
USB_OSCAVDD
(Oscillator analog supply)
1.5V
0
10
0.1
Board EVDD/IVDD
R1
C2
USB VDD Pin
C1
GND
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