參數(shù)資料
型號(hào)： MCF54450VM180
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 180 MHz, RISC PROCESSOR, BGA256
封裝： 17 X 17 MM, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù)： 30/48頁(yè)
文件大?。?/td> 942K
代理商： MCF54450VM180
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
36
5.15
ATA Interface Timing Specifications
The ATA controller is compatible with the ATA/ATAPI-6 industry standard. Refer to the ATA/ATAPI-6 Specficiation and the
ATA controller chapter of the MCF54455 Reference Manual for timing diagrams of the various modes of operation.
The timings of the various ATA data transfer modes are determined by a set of timing equations described in the ATA section
of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet timing. Table 25
provides implementation specific timing parameters necessary to complete the timing equations.
5.16
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the
transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the MCF54455 Reference Manual for information on the modified transfer formats used for communicating
with slower peripheral devices.
Table 25. ATA Interface Timing Specifications1,2
1 These parameters are guaranteed by design and not testable.
2 All timings specified with a capacitive load of 40pF.
Name
Characteristic
Symbol
Min
Max
Unit
Notes
A1
Setup time — ATA_IORDY to SYSCLK falling
tSUI
4.0
—
ns
A2
Hold time — ATA_IORDY from SYSCLK falling
tHI
3.0
—
ns
A3
Setup time — ATA_DATA[15:0] to SYSCLK rising
tSU
4.0
—
ns
A4
Propagation delay — SYSCLK rising to all outputs
tCO
—7.0
ns
3
3 Applies to ATA_CS[1:0], ATA_DA[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA[15:0]
A5
Output skew
tSKEW1
—1.5
ns
A6
Setup time — ATA_DATA[15:0] valid to ATA_IORDY
tI_DS
2.0
—
ns
4
4 Applies to Ultra DMA data-in burst only
A7
Hold time — ATA_IORDY to ATA_DATA[15:0] invalid
tI_DH
3.5
—
ns
Table 26. DSPI Module AC Timing Specifications1
Name
Characteristic
Symbol
Min
Max
Unit
Notes
DS1
DSPI_SCK Cycle Time
tSCK
4 x tSYS
—ns
2
DS2
DSPI_SCK Duty Cycle
—
(tsck ÷ 2) - 2.0
(tsck ÷ 2) + 2.0
ns
3
Master Mode
DS3
DSPI_PCSn to DSPI_SCK delay
tCSC
(2
× t
SYS) - 1.5
—
ns
4
DS4
DSPI_SCK to DSPI_PCSn delay
tASC
(2
× t
SYS) - 3.0
—
ns
5
DS5
DSPI_SCK to DSPI_SOUT valid
—
5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
—
-5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
—
9
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
—
0
—
ns
Slave Mode
DS9
DSPI_SCK to DSPI_SOUT valid
—
10
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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