參數(shù)資料
型號(hào)： MCF54418CMJ250
廠(chǎng)商： Freescale Semiconductor
文件頁(yè)數(shù)： 59/61頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5441x
核心處理器： Coldfire V4
芯體尺寸： 32-位
速度： 250MHz
連通性： 1 線(xiàn)，CAN，EBI/EMI，以太網(wǎng)，I²C，智能卡，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 87
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤(pán)
Hardware design considerations
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
7
Figure 5 shows an example for bypassing the FlexBus power supply for the MPU. This bypass should be applied to as many
FB_VDD signals as routing allows. Each one should be placed as close to the ball as possible.
Figure 5. FB_VDD power filter
2.2
Supply voltage sequencing
Figure 6 shows requirements in the sequencing of the I/O VDD (EVDD), FlexBus VDD (FBVDD), SDRAM VDD (SDVDD), PLL
VDD (VDD_OSC_A_PLL), and internal logic/core VDD (IVDD).
Figure 6. Supply voltage sequencing and separation cautions
The relationships between FBVDD, SDVDD and EVDD are non-critical during power-up and power-down sequences. FBVDD
(1.8 – 3.3V), SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD.
NOTE
All I/O VDD pins must be powered on when the device is functioning, except when in
standby mode.
In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off.
Board 1.8–3.3 V
0.1 F
FB_VDD
1 F
GND
supply
EVDD/FBVDD (3.3V)
IVDD, VDD_OSC_A_PLL
Time
3.3V
1.5V
0
D
C
Po
wer
Su
ppl
y
V
olt
age
Notes:
1 Input voltage must not be greater than the supply voltage (EV
DD, FBVDD, SDVDD, IVDD, or PVDD) by more
than 0.5V at any time, including during power-up.
2 Use 25 V/millisecond or slower rise time for all supplies.
2.5V
SDVDD (2.5V — DDR)
1.8V
SDVDD/FBVDD (1.8V — DDR2)
Supplies stable
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參數(shù)描述
MCF54418CMJ250 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU COLDFIRE 250MHZ 256-MA
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