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MCF5407 User’s Manual
Exception Processing Overview
dened by Motorola; the remaining 192 are user-dened interrupt vectors.
ColdFire processors inhibit sampling for interrupts during the rst instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register.
2.8.1 Exception Stack Frame Denition
The exception stack frame is shown in
Figure 2-1. The rst longword of the exception stack
frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The
second longword contains the 32-bit program counter address.
Table 2-19. Exception Vector Assignments
Vector Numbers
Vector Offset (Hex)
Stacked Program Counter 1
1
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC
of the instruction that immediately follows the instruction that caused the fault.
Assignment
0
000
—
Initial stack pointer
1
004
—
Initial program counter
2
008
Fault
Access error
3
00C
Fault
Address error
4
010
Fault
Illegal instruction
5
014
Fault
Divide by zero
6–7
018–01C
—
Reserved
8
020
Fault
Privilege violation
9
024
Next
Trace
10
028
Fault
Unimplemented line-a opcode
11
02C
Fault
Unimplemented line-f opcode
12
030
Next
Non-PC breakpoint debug interrupt
13
034
Next
PC breakpoint debug interrupt
14
038
Fault
Format error
15
03C
Next
Uninitialized interrupt
16–23
040–05C
—
Reserved
24
060
Next
Spurious interrupt
25–31
064–07C
Next
Level 1–7 autovectored interrupts
32–47
080–0BC
Next
Trap #0–15 instructions
48–60
0C0–0F0
—
Reserved
61
0F4
Fault
Unsupported instruction
62–63
0F8–0FC
—
Reserved
64–255
100–3FC
Next
User-dened interrupts