參數(shù)資料
型號(hào)： MCF5328CVM240J
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 240 MHz, RISC PROCESSOR, PBGA256
封裝： 17 X 17 MM, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù)： 17/50頁(yè)
文件大?。?/td> 1114K
代理商： MCF5328CVM240J
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
24
Figure 9. SDR Write Timing
SD9
SD_DQS[3:2] input hold relative to SD_CLK7
tDQISDCH Does not apply. 0.5×SD_CLK fixed width.
SD10
Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)8
tDVSDCH
0.25
×
SD_CLK
—ns
SD11
Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD12
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
tSDCHDMV
—
0.75
× SD_CLK
+ 0.5
ns
SD13
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
tSDCHDMI
1.5
—
ns
1 The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329
Reference Manual for more information on setting the SDRAM clock rate.
2 SD_CLK is one SDRAM clock in (ns).
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
4 Pulse width high plus pulse width low cannot exceed min and max clock period.
5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
8 Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
Table 10. SDR Timing Specifications (continued)
Symbol
Characteristic
Symbol
Min
Max
Unit
SD_CLK
SDDM
D[31:0]
A[23:0]
SD_BA[1:0]
CMD
ROW
SD1
SD4
COL
SD5
WD1
WD2
WD3
WD4
SD12
SD11
SD_CSn
SD_RAS
SD_WE
SD_CAS
SD2
SD3
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF5327CVM240,
MCF53281CVM240,
MCF5328CVM240,
MCF5329CVM240
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF5329 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
MCF5329_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
MCF5329CVM240 功能描述:IC MCU 32BIT 240MHZ 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MCF532x 標(biāo)準(zhǔn)包裝:330 系列:- 核心處理器:- 芯體尺寸:8/16-位 速度:40MHz 連通性:UART/USART 外圍設(shè)備:DMA，PWM，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:外部程序存儲(chǔ)器 EEPROM 大小:- RAM 容量:- 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-BQFP 包裝:管件
MCF5329CVM240J 功能描述:32位微控制器 - MCU V3CORE RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
MCF5329DS 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:MCF5329 ColdFire Microprocessor Data Sheet
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